An inexpensive and effective experimental model for an educational system of the logic circuit design is developed in this paper. The design of a mininum-cost full adder/substractor by this model illustlates the use of commonly used gates, the synthes...
An inexpensive and effective experimental model for an educational system of the logic circuit design is developed in this paper. The design of a mininum-cost full adder/substractor by this model illustlates the use of commonly used gates, the synthesis of several logic circuits, cost-minimization by real-life criteria.
This model will be appropriate for a labortaory exersice of a senior course for digital engineering students.