1 "Tree-dimensional DIBL for shallow trench isolated MOSFET’s" 46 : 139-, 1999.
2 "Transistor off-state leakage current induced by TiSi2 pre-amorphizing implant in a 0.2 um CMOS process" 21 (21): 155-, 2000.
3 "Low resistivity Tisi 2 on narrow p" 81 (81): 259-, 2002.
4 "Improvement of sub 0.1㎛ VLSI device quality using a novel titanium silicide formation process" 40 (40): 335-, 2002.
5 "Epitaxial Titanium Silicide Islands and Nanowires" 1-3 : 148-, 2003.
6 "Direct tunneling gate current in deep submicron MOSFET’s" 1 : 742-, 2001.
7 "Dielectric breakdown mechanism of thin SiO2 studied by the post break-down resistance statistics" 47 (47): 741-, 2000.
8 "A study on improvement of 30 Å ultra thin gate oxide quality" 729-, 2004.
9 "A study of metal impurities behavior due to difference in isolation structure on ULSI devices" 4 (4): 5900-, 2002.
10 "A new method of thin gate SiO2 reliability characterization" 34 (34): 437-, 2002.
1 "Tree-dimensional DIBL for shallow trench isolated MOSFET’s" 46 : 139-, 1999.
2 "Transistor off-state leakage current induced by TiSi2 pre-amorphizing implant in a 0.2 um CMOS process" 21 (21): 155-, 2000.
3 "Low resistivity Tisi 2 on narrow p" 81 (81): 259-, 2002.
4 "Improvement of sub 0.1㎛ VLSI device quality using a novel titanium silicide formation process" 40 (40): 335-, 2002.
5 "Epitaxial Titanium Silicide Islands and Nanowires" 1-3 : 148-, 2003.
6 "Direct tunneling gate current in deep submicron MOSFET’s" 1 : 742-, 2001.
7 "Dielectric breakdown mechanism of thin SiO2 studied by the post break-down resistance statistics" 47 (47): 741-, 2000.
8 "A study on improvement of 30 Å ultra thin gate oxide quality" 729-, 2004.
9 "A study of metal impurities behavior due to difference in isolation structure on ULSI devices" 4 (4): 5900-, 2002.
10 "A new method of thin gate SiO2 reliability characterization" 34 (34): 437-, 2002.
11 "A Study on improvement of sub 0.1㎛ VLSI CMOS device ultra thin gate oxide quality using a novel STI structure" 13 (13): 729-, 2000.