Design of Next Generation Amplifiers Using Nanowire FETs

다국어 초록 (Multilingual Abstract)

Vertical nanowire SGFETs (Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10㎚ channel length and a 2㎚ channel radius. The amplifier dissipates 5㎼ power and provides 5㎔ bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40㏈m and -52㏈m, respectively, and the 3rd order intermodulation is -24㏈m for a two-tone input signal with 10㎷ amplitude and 10㎓ frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

목차 (Table of Contents)

• Abstract
• 1. Introduction
• 2. High Frequency Modeling
• 3. High Frequency Modeling
• 4. Postlayout Characteristics
• 5. Conclusions
• References

참고문헌 (Reference)

1 A. Bindal, "The Design of Dual Work Unction CMOS Transistors and Circuits Using Silicon Nan-Wire Technology" 6 : 291-302, 2007

2 B. Heydari, "Millimeter-Wave Devices and Circuit Blocks up to104GHz in 90nm CMOS" 42 : 2893-2903, 2007