<P>Computer systems using DRAM are exposed to row-hammering attacks, which can flip data in a DRAM row without directly accessing a row but by frequently activating its adjacent ones. There have been a number of proposals to prevent row-hammerin...
http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
https://www.riss.kr/link?id=A107509140
2018
-
SCOPUS,SCIE
학술저널
96-99(4쪽)
0
상세조회0
다운로드다국어 초록 (Multilingual Abstract)
<P>Computer systems using DRAM are exposed to row-hammering attacks, which can flip data in a DRAM row without directly accessing a row but by frequently activating its adjacent ones. There have been a number of proposals to prevent row-hammerin...
<P>Computer systems using DRAM are exposed to row-hammering attacks, which can flip data in a DRAM row without directly accessing a row but by frequently activating its adjacent ones. There have been a number of proposals to prevent row-hammering, but they either incur large area/performance overhead or provide probabilistic protection. In this paper, we propose a new row-hammering mitigation mechanism named <B>T</B>ime <B>Wi</B>ndow <B>C</B> ount<B>e</B>r based row refresh (TWiCe) which prevents row-hammering by using a small number of counters without performance overhead. We first make a key observation that the number of rows that can cause flipping their adjacent ones (aggressor candidates) is limited by the maximum values of row activation frequency and DRAM cell retention time. TWiCe exploits this limit to reduce the required number of counter entries by counting only actually activated DRAM rows and periodically invalidating the entries that are not activated frequently enough to be an aggressor. We calculate the maximum number of required counter entries per DRAM bank, with which row-hammering prevention is guaranteed. We further improve energy efficiency by adopting a pseudo-associative cache design to TWiCe. Our analysis shows that TWiCe incurs no performance overhead on normal DRAM operations and less than 0.7 percent area and energy overheads over contemporary DRAM devices.</P>
A Scalable HW-Based Inline Deduplication for SSD Arrays
SimpleSSD: Modeling Solid State Drives for Holistic System Simulation
SSD Performance Modeling Using Bottleneck Analysis
Partitioning Compute Units in CNN Acceleration for Statistical Memory Traffic Shaping