광대역 전디지털 클록 데이터 복원회로 설계

다국어 초록 (Multilingual Abstract)

This paper is proposed all digital wide?range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per 2π/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13㎛ CMOS process and verified simulation to spectre tool.

목차 (Table of Contents)

• Abstract
• 1. 서론
• 2. 본론
• 3. 모의실험 및 고찰
• 4. 결론
• 감사의 글
• 참고문헌
• 저자소개

참고문헌 (Reference)

1 R. B. Staszewski, "All-Digital TX Frequency synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS" 39 (39): 2278-2291, 2004

2 Fuji Yang, "A CMOS Low-Power Multiple 2.5-3.125-Gb/s Serial Link Macrocell for High IO Bandwidth Network ICs" 37 (37): 1813-1821, 2002

3 Y. S. Seo, "A 5-Gbit/s Clock- and Data-Recovery Circuit with 1/8-Rate Linear Phase Detector in 0.18-um CMOS Technology" 56 (56): 2009

4 Y. S. Abdalla, "A 4Gb/s 1:16 DEMUX Using An All-Static 0.18-um CMOS Logic" 9-11, 2003

5 S. J. Song, "A 0.2-mW2-Mb/s Digital Transceiver Based on WidebandSignaling for Human Body Communications" 42 (42): 2021-2034, 2007

6 S. Y. Lee, "250 Mbps.5 Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13 m CMOS" 185-188, 2010