1 "XC5200 Series Field Programmable Gate Arrays Databook ver 5.2" Xilinx Inc Nov.,1998
2 "Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers" 48 (48): June,1999
3 "Static and Dynamic Configurable Systems" 48 (48): June,1999
4 "Reconfigurable Computing:A survey of Systems and Software" 34 (34): 171-210, June2002.
5 "On the Viability of FPGA-Based Integrated Coprocessors" 206-215, Apr.,1996.
6 "Java-based programmable networked embedded system architecture with multiple application support" International Conference on Chip Design Automation 448-451, Aug.,2000
7 "Hardware Software Partitioning for Multifunction Systems" In Proceedings of International Conference on Computer Aided Design 516-521, Nov.,1997
8 "Hardware Software Partitioning and Pipelining" 713-716, 1997
9 "Guest Editors’ Introduction" 48 (48): 1999
10 "Design Space Exploration of Stream- based Dataflow Architectures" Delft University of Technology, Netherlands 1998
1 "XC5200 Series Field Programmable Gate Arrays Databook ver 5.2" Xilinx Inc Nov.,1998
2 "Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers" 48 (48): June,1999
3 "Static and Dynamic Configurable Systems" 48 (48): June,1999
4 "Reconfigurable Computing:A survey of Systems and Software" 34 (34): 171-210, June2002.
5 "On the Viability of FPGA-Based Integrated Coprocessors" 206-215, Apr.,1996.
6 "Java-based programmable networked embedded system architecture with multiple application support" International Conference on Chip Design Automation 448-451, Aug.,2000
7 "Hardware Software Partitioning for Multifunction Systems" In Proceedings of International Conference on Computer Aided Design 516-521, Nov.,1997
8 "Hardware Software Partitioning and Pipelining" 713-716, 1997
9 "Guest Editors’ Introduction" 48 (48): 1999
10 "Design Space Exploration of Stream- based Dataflow Architectures" Delft University of Technology, Netherlands 1998
11 "An approach for quantitative analysis of application-specific dataflow architectures" Architectures and Processors (ASAP’97) Zurich, Switzerland 338-349, 1997