In this paper, the clock and data recovery circuit using Coarse/Fine Loop is proposed for achieving fast Locking. the part of locking the frequency in CDR is composed of two Loop : Coarse Loop and Fine Loop. Each Loop is designed separate phase freque...
In this paper, the clock and data recovery circuit using Coarse/Fine Loop is proposed for achieving fast Locking. the part of locking the frequency in CDR is composed of two Loop : Coarse Loop and Fine Loop. Each Loop is designed separate phase frequency and charge pump and Phase Detector part using 4X oversampling method operate near Locking condition. It operates at 3.125Gbps and jitter is 50㎰. Total CDR is designed a 0.18 CMOS technology. total power consumption is 150㎽.