ATM 스위치에서 셀 순서 재 정렬 방식에 관한 연구 = (A) Study on the Cell Resequence Method of the ATM Switch

다국어 초록 (Multilingual Abstract)

The future B-ISDN(Broadband Integrated Services Digital Network) will support a wide variety of communication services with different QoS (Quality of Services) requirements The ATM(Asynchronous Transfer Mode), because of its efficiency and flexibility, is widely accepted as the basis for the future B-ISDN
Recently, research and development for realizing commercial ATM switching systems for broadband ISDN have been active worldwide.
One of the important issue in these activities is the design issue of ATM switch fabrics that is related to the speed The ATM switches are required to support lines at the speeds of several Gbps It is expected that ATM switch fabrics will be implemented using very high-speed devices including those for the optical switching and highly parallel processing architectures with latest VLSI technologies.
But the parallel switch architecture has the out-of-sequence problem To solve this problem, the time-stamp method and the cell sequence aligning memory method were proposed by NEC Corporation. But the former has unnecessary delay time to resequence, and the latter has the continuous out-of-sequence which is occurred by the signal loss between the cell counter and the comparator, by the overflow because of the fixed buffer size
We have studied the out-of-sequence problem due to the cell transfer delay and the overflow due to the diffident cell transfer delay for the parallel ATM switch fabric and the fixed buffer size in the switch fabric Then, we propose the new ATM switch architecture to fix the out-of-sequence in the parallel ATM switch fabric Also, we solve two problems in the parallel ATOM switch using the time-stamp method and the cell sequence aligning memory method.

목차 (Table of Contents)

• 목차 = ⅰ
• 그림목차 = ⅲ
• ABSTRACT = ⅴ
• Ⅰ. 서론 = 1
• Ⅱ. ATM스위치 특성 = 5
• A. 기본 원리 = 5
• B. 스위치 요구 파라미터 = 7
• C. 버퍼링 방식 = 10
• Ⅲ. 공통버퍼형 ATM스위치 = 14
• A. 스위치의 구성 = 14
• B. 스위치의 동작 = 15
• C.스위치의 특성 = 16
• D. 병렬 스위치 구조를 갖는 공통버퍼형 ATM스위치 = 17
• 1. 스위치의 구성 = 17
• 2. 스위치의 동작 = 17
• 3. 스위치의 특징 = 18
• Ⅳ. 셀 순서 재 정렬부를 갖는 ATM스위치 = 19
• A. Time-stamp 방식을 이용한 병렬 ATOM스위치 = 19
• 1. 스위치의 구성 = 19
• 2. 스위치의 동작 = 20
• 3. 스위치의 특징 = 21
• B. 셀 순서 정렬 메모리 방식을 이용한 병렬 ATM스위치 = 22
• 1. 스위치의 구성 = 22
• 2. 스위치의 동작 = 22
• 3. 스위치의 특징 = 24
• Ⅴ. ATM스위치에서 순서 재 정렬 방식의 제안 = 26
• A. 스위치의 구성 = 26
• B. 각 부별 동작 = 28
• 1. 분배부 = 28
• 2. 스위치부 = 28
• 3. 셀 순서 재 정렬부 = 29
• Ⅶ. 시뮬레이션 및 결과 분석 = 39
• A. 트래픽 모델링 = 39
• B. 시뮬레이션 결과 및 분석 = 39
• Ⅳ. 결론 = 45
• 참고문헌 = 46