A Study on Low-Temperature Growth and Property Optimization of High-Ge-Content Si₁??Ge? Epitaxial Layers for Enhanced Reliability in Next-Generation Semiconductor Devices

다국어 초록 (Multilingual Abstract)

A Study on Low-Temperature Growth and Property Optimization of High-Ge-Content Si₁₋ₓGeₓ Epitaxial Layers for Enhanced Reliability in Next-Generation Semiconductor Devices Ji-Hoon Kim Department of Electronic Engineering Graduate School of Hanyang University Advised by Prof. Jin-Sub Park The advancement of semiconductor technology necessitates innovative materials and processes to overcome the limitations of conventional CMOS technology while achieving higher integration density and performance. In next-generation devices such as Fin Field- Effect Transistors (FETs), Gate-All-Around (GAA) structures, and 3D Dynamic Random- Access Memory (DRAM), Si₁₋ₓGeₓ epitaxial layers have emerged as key materials due to their high mobility, strain engineering benefits, and compatibility with existing semiconductor processes. However, the growth of defect-free, high-Ge-content Si₁₋ₓGeₓ layers at low temperatures remains a significant challenge. This study addresses these challenges by investigating the low-temperature growth and property optimization of high-Ge-content Si₁₋ₓGeₓ layers using an ultra-high vacuum chemical vapor deposition (UHV-CVD) system equipped with an Oxide Elimination Chamber (OEC). This research focused on three main objectives. First, to develop a low-temperature process for growing high-Ge-content Si₁₋ₓGeₓ layers with Ge concentrations exceeding 45 at%, enabling defect-free epitaxial layers for semiconductor applications. Second, to identify optimal pre-treatment methods for native oxide removal without relying on WET etching, ensuring clean surfaces for epitaxial growth. Third, to optimize selective growth processes by comparing Co-flow and CGE methods and determining the ideal gas flow and etching ratios to enhance layer uniformity and selectivity. The results demonstrated that by optimizing the growth temperature (450-530°C) and gas ratio (Si₂H₆:GeH4 = 1:7.5), defect-free Si₁₋ₓGeₓ layers with a Ge concentration of 45.9 at% were successfully achieved. Additionally, a B₂H₆ flow rate of 50 sccm resulted in a boron doping concentration of 2.7 × 10²⁰ atoms/cm³ with a surface roughness of 0.11 nm. Selective growth was achieved at a Cl₂ flow rate of 4 sccm in the Co-flow method and a growth-to-etch ratio of 1:1 in the CGE method. Furthermore, the study of GeH₄ injection methods (Continuous, Step, and Ramping) revealed that the Continuous method provided uniform Ge concentrations, while the Step and Ramping methods effectively controlled Ge concentration gradients within the layer. This study demonstrates the feasibility of low-temperature growth and optimization of high-Ge-content Si₁₋ₓGeₓ layers, overcoming the limitations of conventional processes. The findings provide a foundation for integrating these layers into advanced semiconductor devices, including multi-layer 3D structures. Moreover, the selective growth and doping methodologies presented in this study can be directly applied to practical semiconductor applications, such as logic and memory devices, significantly enhancing their reliability and performance. By advancing the understanding of Si₁₋ₓGeₓ materials and processes, this research paves the way for future innovations in semiconductor technology. Keywords: Si₁₋ₓGeₓ, epitaxial growth, low-temperature process, selective growth, boron doping, UHV-CVD, Oxide Elimination Chamber (OEC), next-generation semiconductors.

목차 (Table of Contents)

• Table of Contents i
• Abstract iii
• LIST OF FIGURES vi
• LIST OF TABLES ix
• Abbreviations x
• CHAPTER 1. INTRODUCTION １
• 1.1 Background and Motivation １
• 1.2 Objectives and Contributions ７
• References ９
• CHAPTER 2. LITERATURE REVIEW １０
• 2.1 Overview of Epitaxial Si₁₋ₓGeₓ Technology １０
• 2.2 Challenges in Low-Temperature Growth １２
• 2.3 Boron Doping and Surface Roughness Control １４
• 2.4 Summary １７
• References １８
• CHAPTER 3. EXPERIMENTAL METHODOLOGY １９
• 3.1 UHV-CVD System and Process Design １９
• 3.2 Oxide Removal and Surface Preparation ２１
• 3.3 Optimization of Growth Parameters ２２
• 3.4 Analytical Techniques ２４
• 3.5 Summary ２６
• CHAPTER 4. RESULTS AND DISCUSSION ２７
• 4.1 Influence of Growth Temperature and Native Oxide Removal Techniques on
• Ge Incorporation and Defect Suppression in Si1-xGex Layers ２７
• 4.2 Effect of Gas Ratios on Growth Rate and Surface Roughness ３７
• 4.3 Impact of Boron Doping on Electrical and Structural Properties ４３
• 4.4 Optimization of Selective Si₁₋ₓGeₓ Epitaxial Growth: Effects of Cl₂ Flow
• Rate, Growth-to-Etch Time Ratio, and GeH₄ Supply Methods ４７
• 4.5 Summary ５４
• References ５６
• CHAPTER 5. CONCLUSION AND FUTURE WORK ５７
• 5.1 Conclusion ５７
• 5.2 Future Work ６０
• 5.3 Final Remarks` ６２
• List of Publications ６６
• International Journals ６６
• International Conferences ６７
• ABSTRACT (IN KOREAN) ６８