Fabrication and Process Simulation of SOI MOSFETs with a 30-nm Gate Length

다국어 초록 (Multilingual Abstract)

We have obtained systematic simulation and experimental results for 30-nm-gate-length metaloxide-
semiconductor eld-eect transistor (MOSFET) fabricated on ultra-thin silicon-on-insulator
(SOI) substrates. The two-dimensional process simulation and the device simulation were carried
out to optimize the fabrication process conditions and the device characteristics of 30-nm-gatelength
SOI MOSFETs. A new simple source/drain formation technique using the solid-phase diffusion
(SPD) method was developed. Based on the simulation results and the SPD ultra-shallow
junction formation technique, we successfully fabricated 30-nm-gate-length SOI nMOSFETs. The
experimental results for the 30-nm-gate-length SOI nMOSFETs showed good transistor behaviors
and superior device scalability.