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    RISC 프로세서용 고속 레지스터 파일의 ASIC 설계 = ASIC Design of High Speed Register File for RISC Processor

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    https://www.riss.kr/link?id=A19707099

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    Modular memory is an essential component of any digital IC design library. The major application of high speed rcgister file has been as the main memory of large-scale computers, super computer, microcomputer, workstation, so on.
    So, in the thesis, The deigned high speed register file for RISC processor, which is possivle to processing concurrent I/O by separating read/write bitline and word access TR has become one of the key embedded elements for processor VLSI's, because it allows simultaneous access from multiple resource and the parallel operations yield a high system throughput. Benefits include reduced constraints on the client units and simpler resister to resister programming models. Stable output characteristics was obtained by testing at peripheral of operation and was designed by using 1.2[μm] CMOS design rule.

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    Modular memory is an essential component of any digital IC design library. The major application of high speed rcgister file has been as the main memory of large-scale computers, super computer, microcomputer, workstation, so on. So, in the thesis, T...

    Modular memory is an essential component of any digital IC design library. The major application of high speed rcgister file has been as the main memory of large-scale computers, super computer, microcomputer, workstation, so on.
    So, in the thesis, The deigned high speed register file for RISC processor, which is possivle to processing concurrent I/O by separating read/write bitline and word access TR has become one of the key embedded elements for processor VLSI's, because it allows simultaneous access from multiple resource and the parallel operations yield a high system throughput. Benefits include reduced constraints on the client units and simpler resister to resister programming models. Stable output characteristics was obtained by testing at peripheral of operation and was designed by using 1.2[μm] CMOS design rule.

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