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      고속의 암호칩 구현을 위한 파이프라인드 설계 방법 = A Pipelined Design Methodology for High Performance Cryptography Chip

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      https://www.riss.kr/link?id=A35501112

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      Symmetric key cryptography algorithms are continuous repeating process of transpose and transposition, and have four modes of CBC, ECB, CFB, and OFB according to the operation methodology. Also, the algorithms have a number of computation because final cryptography sentences in the algorithm are internally accomplished by the various round of repeating computation. In this paper, we propose the pipelined design methodology to accelerate the cryptography operation in the ECB mode of block cryptography algorithm. In the proposed method, we implemented cryptography operation block of many rounds and can extremely improve overall operational speed because the method is continuously executed. As the results of estimation after designing the cryptography chip by pipelened structure, several tens of improved performance in the case of 3DES is possible, but we have known the generating of disadvantage that the chip size is increased.
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      Symmetric key cryptography algorithms are continuous repeating process of transpose and transposition, and have four modes of CBC, ECB, CFB, and OFB according to the operation methodology. Also, the algorithms have a number of computation because fina...

      Symmetric key cryptography algorithms are continuous repeating process of transpose and transposition, and have four modes of CBC, ECB, CFB, and OFB according to the operation methodology. Also, the algorithms have a number of computation because final cryptography sentences in the algorithm are internally accomplished by the various round of repeating computation. In this paper, we propose the pipelined design methodology to accelerate the cryptography operation in the ECB mode of block cryptography algorithm. In the proposed method, we implemented cryptography operation block of many rounds and can extremely improve overall operational speed because the method is continuously executed. As the results of estimation after designing the cryptography chip by pipelened structure, several tens of improved performance in the case of 3DES is possible, but we have known the generating of disadvantage that the chip size is increased.

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