This paper proposes a counter structure for low-power single-slope ADC (SSADC) operation of a CMOS Image Sensor (CIS). This work minimized power consumption by tweaking the operation of the LSB flipflop and LSB+1 flipflop. The proposed counter was con...
This paper proposes a counter structure for low-power single-slope ADC (SSADC) operation of a CMOS Image Sensor (CIS). This work minimized power consumption by tweaking the operation of the LSB flipflop and LSB+1 flipflop. The proposed counter was confirmed to have a power saving effect of 62.5% compared to the conventional counter through simulation. This work is expected to contribute to low-power SSADC design.