Design Optimization of the Arithmatic Logic Unit Circuit for the Processor to Determine the Number of Errors in the Reed Solomon Decoder

국문 초록 (Abstract)

본 논문에선 리드 솔로몬 복호기의 오류갯수를 판별하는 마이크로콘트롤러의 새로운 설계법을 제시한다. 본 설계법을 통해 기존보다 빠르고 훨씬 회로량이 줄어든 최적화된 오류갯수 판별기용 산술논리연산장치회로를 설계할 수 있었다. 이 리드솔로몬 복호기는 거의 모든 디지털 통신 및 가전기기의 데이터 보존기기의 보호장치로 사용되어질 수 있다. 여기서는 제곱계산회로의 최소화가 가능해 병렬처리를 통해 오류갯수 판별기의 최적화를 이룰 수 있었다.

다국어 초록 (Multilingual Abstract)

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

참고문헌 (Reference)

1 Pusan Patel, "Parallel Multiplier Designs for the Galois/Counter Mode of Operation" Univ. of Wateroo Canada 2008

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5 Ming Jang, "Implementation of Switch box Using a Subfield"

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7 T.K. Moon, "Error Correction Coding: Mathematical Methods and Algorithms" John Wiley & Sons,Inc 2005

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9 D. Canright, "Avoid Mask Re-use in Galois Multipliers" 2008

10 Joschi Brauchle, "A Systematic Reed-Solomon Encoder with Arbitrary Parity Positions" 2009