1 G. Larrieu, "Vertical nanowire array-based field effect transistors for ultimate scaling" 5 (5): 2437-2441, 2013
2 E. J. Nowak, "Turning silicon on its edge [double gate CMOS/FinFET technology]" 20 (20): 20-31, 2004
3 M. Bohr, "The evolution of scaling from the homogeneous era to the heterogeneous era" 1-1, 2011
4 "Sentaurus, ver. M-2016"
5 "Sentaurus Application note, [Online]"
6 D. E. Nikonov, "Overview of beyond-CMOS devices and a uniform methodology for their benchmarking" 101 (101): 2498-2533, 2013
7 "ITRS 2.0 2015, Beyond CMOS, [Online]"
8 Y. Taur, "Fundamental of Modern VLSI Devices" Cambridge Univ. Press 2013
9 R. Huang, "Challenges of 22 nm and beyond CMOS technology" 52 (52): 1491-1533, 2009
10 H. M. Fahad, "Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?" 2 (2): 2012
1 G. Larrieu, "Vertical nanowire array-based field effect transistors for ultimate scaling" 5 (5): 2437-2441, 2013
2 E. J. Nowak, "Turning silicon on its edge [double gate CMOS/FinFET technology]" 20 (20): 20-31, 2004
3 M. Bohr, "The evolution of scaling from the homogeneous era to the heterogeneous era" 1-1, 2011
4 "Sentaurus, ver. M-2016"
5 "Sentaurus Application note, [Online]"
6 D. E. Nikonov, "Overview of beyond-CMOS devices and a uniform methodology for their benchmarking" 101 (101): 2498-2533, 2013
7 "ITRS 2.0 2015, Beyond CMOS, [Online]"
8 Y. Taur, "Fundamental of Modern VLSI Devices" Cambridge Univ. Press 2013
9 R. Huang, "Challenges of 22 nm and beyond CMOS technology" 52 (52): 1491-1533, 2009
10 H. M. Fahad, "Are nanotube architectures more advantageous than nanowire architectures for field effect transistors?" 2 (2): 2012