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Design and Implementation of the Message-Driven Processor
Dally, W. J.; Ahmed, S.; Carrick, P.; Chien, A. MIT 1992 p.5-25
TRIPTYCH: An FPGA Architecture with Integrated Logic and Routing
Hauck, S.; Borriello, G.; Ebeling, C. MIT 1992 p.26-43
Reducing Multi-Processor Memory Contention with Orthogonal Redundant Memory
Berger, R. MIT 1992 p.44-57
A New Method to Compute Prime and Essential Prime Implicants of Boolean Functions
Coudert, O.; Madre, J. C. MIT 1992 p.113-128
Equation-Free Synthesis of High-Performance Linear Analog Circuits
Ochotta, E. S.; Rutenbar, R. A.; Carley, L. R. MIT 1992 p.129-146
A CMOS Parallel Adder Using Wave Pipelining
Fan, D.; Gray, C. T.; Farlow, W.; Hughes, T. MIT 1992 p.147-164
Using Qualified Clocks in the NORA Clocking Methodology to Implement a Systolic Queue Design
Dickey, S. R.; Kenner, R. MIT 1992 p.165-179