다결정 실리콘 박막트랜지스터의 제작을 위한 3-마스크 공정의 개발 = The Development of 3-Mask Process for Fabrication of Polycrystalline Silicon Thin Film Transistor

다국어 초록 (Multilingual Abstract)

In this study, we developed the 3-mask process for fabrication of polycrystalline thin film transistor and had a focus on optimization of process, Three masks used to fabricate devices are for passivation oxide, for active area, and for electrodes. Minimum line width is 10μm in our process. The size of gate of thin film transistor is a 100×30μm2 or a 200×60μm2. And these devices have a similiar electrical characteristics, about 5.7cm2/v · s of mobility, 15V of threshold voltage, and 104~105 level of on/off ratios. If the 3-mask process includes the recrystallization and hydrogenation process, the electrical characteristics of devices will be improved significantly. Especially, we took full advantages on the process equipments for MOSFET fabrication and used only three masks for fabricating devices. It is expected that the 3-mask process for thin film transistor can be employed in the small-scale semiconductor process for education.

목차 (Table of Contents)

• ABSTRACT
• I. 서론
• II. 실 험
• III. 실험결과의 평가 및 고찰
• IV. 결 론
• 참 고 문 헌