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RISS 인기검색어

A <tex> $\hbox{Gb/s}+$</tex> Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time

한글로보기

https://www.riss.kr/link?id=A107584708

저자

Young-Ho Kwak ; Inhwa Jung ; Chulwoo Kim
발행기관
IEEE
학술지명
IEEE Transactions on Circuits and Systems II: Express Briefs
권호사항

Vol.57 No.2 [2010]
발행연도
2010
작성언어
-
등재정보
SCI,SCIE,SCOPUS
자료형태
학술저널
수록면

120-125(6쪽)
제공처
ScienceON
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다국어 초록 (Multilingual Abstract)

This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18-¿m CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.1-3.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.

번역하기

This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18-¿m CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signa...

This brief introduces a low-noise slew-rate/impedance-controlled high-speed output driver in 0.18-¿m CMOS process. The output driver adopts an open-loop structure that enables the system to take only a single cycle to control the signal slew-rate or driver impedance. The control blocks consume 4.907 mA at 1 Gb/s. The proposed output driver is designed to maintain the data slew rate in the range of 2.1-3.6 V/ns. The proposed scheme is also applied to a pseudo-open-drain output driver, and the maximum and minimum variations of the impedance are +1.78% and -1.30%, respectively.