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    KCI등재 SCIE SCOPUS

    3D Compositional Characterization of Si/SiO2 Vertical Interface Structure by Atom Probe Tomography

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    https://www.riss.kr/link?id=A105872583

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    다국어 초록 (Multilingual Abstract) kakao i 다국어 번역

    Precise interpretation of three-dimensional atom probe tomography (3D-APT) data is necessary to reconstruct semiconductor-device structures. In particular, it is difficult to reconstruct the hetero-structure of conductors and insulators using APT analysis, due to the preferential evaporation of low-evaporation field-material. In this paper,shallow-trench isolation (STI) structure, consisting of a Si column and a SiO2 region, is analyzed using APT. The dimensional artifact known as the local-magnification-effect occurring as a result of the geometric deviation from the ideal hemisphere was successfully calibrated by ‘high-angle annular dark-field (HAADF) scanning transmission electron microscopy (STEM) tomography’ and Electron Energy Loss Spectroscopy (EELS). In the direction of the width, the Si layer was compressed by 50%, and the interface was expanded by 250% with respect to the reference data obtained for the same sample. A 5-nm-thick transition layer was observed at the interface between Si and SiO2. The composition of the transition layer follows the well-developed sequence Si-Si2O-SiO-SiO2 from the Si area to the SiO2 area. Atoms at the interface were likely to evaporate with a bit wider angle than atoms in the Si area due to the preferentially evaporated Si layer, which caused the interface area to appear locally magnified.
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    Precise interpretation of three-dimensional atom probe tomography (3D-APT) data is necessary to reconstruct semiconductor-device structures. In particular, it is difficult to reconstruct the hetero-structure of conductors and insulators using APT anal...

    Precise interpretation of three-dimensional atom probe tomography (3D-APT) data is necessary to reconstruct semiconductor-device structures. In particular, it is difficult to reconstruct the hetero-structure of conductors and insulators using APT analysis, due to the preferential evaporation of low-evaporation field-material. In this paper,shallow-trench isolation (STI) structure, consisting of a Si column and a SiO2 region, is analyzed using APT. The dimensional artifact known as the local-magnification-effect occurring as a result of the geometric deviation from the ideal hemisphere was successfully calibrated by ‘high-angle annular dark-field (HAADF) scanning transmission electron microscopy (STEM) tomography’ and Electron Energy Loss Spectroscopy (EELS). In the direction of the width, the Si layer was compressed by 50%, and the interface was expanded by 250% with respect to the reference data obtained for the same sample. A 5-nm-thick transition layer was observed at the interface between Si and SiO2. The composition of the transition layer follows the well-developed sequence Si-Si2O-SiO-SiO2 from the Si area to the SiO2 area. Atoms at the interface were likely to evaporate with a bit wider angle than atoms in the Si area due to the preferentially evaporated Si layer, which caused the interface area to appear locally magnified.

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    참고문헌 (Reference)

    1 X. Li, 692-, 2009

    2 F. Vurpillot, 76 : 3127-, 2000

    3 G. P. Lansbergen, 4 : 656-, 2008

    4 D. A. Muller, 399 : 758-, 1999

    5 G. R. Harp, 31 : 23-, 1990

    6 P. E. Batson, 366 : 727-, 1993

    7 C. Oberdorfer, 17 : 15-, 2011

    8 T. F. Kelly, 37 : 681-, 2007

    9 S. Koelling, 111 : 540-, 2011

    10 A. Morley, 109 : 535-, 2009

    1 X. Li, 692-, 2009

    2 F. Vurpillot, 76 : 3127-, 2000

    3 G. P. Lansbergen, 4 : 656-, 2008

    4 D. A. Muller, 399 : 758-, 1999

    5 G. R. Harp, 31 : 23-, 1990

    6 P. E. Batson, 366 : 727-, 1993

    7 C. Oberdorfer, 17 : 15-, 2011

    8 T. F. Kelly, 37 : 681-, 2007

    9 S. Koelling, 111 : 540-, 2011

    10 A. Morley, 109 : 535-, 2009

    11 M. Muller, 111 : 064908-, 2012

    12 Jang-Sik Lee, "Nano-Floating Gate Memory Devices" 대한금속·재료학회 7 (7): 175-184, 2011

    13 Seung-Chul Song, "Advanced Source and Drain Technologies for Low Power CMOS at 22/20 nm Node and Below" 대한금속·재료학회 7 (7): 277-285, 2011

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    학술지 이력

    학술지 이력
    연월일 이력구분 이력상세 등재구분
    학술지등록 한글명 : Electronic Materials Letters
    외국어명 : Electronic Materials Letters
    2023 평가 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
    2020-01-01 등재 등재학술지 유지 (해외등재 학술지 평가) KCI등재
    2013-10-01 등재 등재학술지 선정 (기타) KCI등재
    2011-01-01 등재 등재후보학술지 유지 (기타) KCI등재후보
    2009-12-29 학회명변경 한글명 : 대한금속ㆍ재료학회 -> 대한금속·재료학회 KCI등재후보
    2008-01-01 등재 SCIE 등재 (신규평가) KCI등재후보
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    학술지 인용정보

    학술지 인용정보
    기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
    2016 1.68 0.41 1.08
    KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
    0.89 0.83 0.333 0.06
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