Inherent variations and the challenge of leakage current control in today’s silicon-on-insulator metal–oxide–semiconductor field-effect transistor limits the scaling of static random-access memory. The fin-shaped field-effect transistor has been...
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https://www.riss.kr/link?id=A107949130
Gurpurneet Kaur (I. K. Gujral Punjab Technical University) ; Sandeep Singh Gill (National Institute of Technical Teachers Training and Research) ; Munish Rattan (Guru Nanak Dev Engineering College)
2021
English
KCI등재,SCOPUS,ESCI
학술저널
774-785(12쪽)
0
0
상세조회0
다운로드다국어 초록 (Multilingual Abstract)
Inherent variations and the challenge of leakage current control in today’s silicon-on-insulator metal–oxide–semiconductor field-effect transistor limits the scaling of static random-access memory. The fin-shaped field-effect transistor has been...
Inherent variations and the challenge of leakage current control in today’s silicon-on-insulator metal–oxide–semiconductor field-effect transistor limits the scaling of static random-access memory. The fin-shaped field-effect transistor has been considered an attractive device for designing low power SRAM cells. In this work, a 14 nm gate length FinFET device has been designed with lanthanum doped zirconium oxide as a compound gate dielectric material. The diminished subthreshold swing (60 mV/dec), reduced leakage current (10 –14 ), lowered drain induced barrier lowering (10.6 mV/V), enhanced drive current (3.74 × 10 –5 ), and increased g m (2.27 × 10 –4 ) were observed after simulating this optimized device. Further, two SRAM cells based on the improved device were implemented with different fin configurations. The stability parameters were investigated with the butterfly curve method. The SRAM Cell-I has presented better read static noise margin and write static noise margin in comparison to the SRAM Cell-II. The impact of supply voltage variations on stability metrics and leakage power has also been presented.
참고문헌 (Reference)
1 "Wikipedia 14nm process"
2 Suzuki, M., "Ultra-thin (EOT= 3A) and low leakage dielectrics of La-aluminate directly on Si substrate fabricated by high temperature deposition" 2005
3 S. Stemmer, "Thermodynamic considerations in the stability of binary oxides for alternative gate dielectrics in complementary metal-oxide–semiconductors" 22 (22): 791-800, 2004
4 B. Cheng, "The impact of highgate dielectrics and metal gate electrodes on sub-100 nm MOSFET’s" 46 (46): 1537-1544, 1999
5 C. Zhao, "Ternary rare-earth metal oxide high-k layers on silicon oxide" 86 (86): 132903-, 2005
6 D. Nirmal, "Subthreshold analysis of nanoscale FinFETs for the ultra-low-power application using high-k materials" 100 (100): 803-817, 2013
7 A. B. Sachid, "Sub-20 nm gate length FinFET design:Can high-κ spacers make a diff erence?" IEEE 1-4, 2008
8 S. Park, "Sol-gel metal oxide dielectrics for all-solution-processed electronics" 114 : 1-22, 2017
9 R. Merritt, "Semiconductor Tops Intel with EUV SRAM"
10 A. Carlson, "SRAM read/write margin enhancements using FinFETs" 18 (18): 887-900, 2010
1 "Wikipedia 14nm process"
2 Suzuki, M., "Ultra-thin (EOT= 3A) and low leakage dielectrics of La-aluminate directly on Si substrate fabricated by high temperature deposition" 2005
3 S. Stemmer, "Thermodynamic considerations in the stability of binary oxides for alternative gate dielectrics in complementary metal-oxide–semiconductors" 22 (22): 791-800, 2004
4 B. Cheng, "The impact of highgate dielectrics and metal gate electrodes on sub-100 nm MOSFET’s" 46 (46): 1537-1544, 1999
5 C. Zhao, "Ternary rare-earth metal oxide high-k layers on silicon oxide" 86 (86): 132903-, 2005
6 D. Nirmal, "Subthreshold analysis of nanoscale FinFETs for the ultra-low-power application using high-k materials" 100 (100): 803-817, 2013
7 A. B. Sachid, "Sub-20 nm gate length FinFET design:Can high-κ spacers make a diff erence?" IEEE 1-4, 2008
8 S. Park, "Sol-gel metal oxide dielectrics for all-solution-processed electronics" 114 : 1-22, 2017
9 R. Merritt, "Semiconductor Tops Intel with EUV SRAM"
10 A. Carlson, "SRAM read/write margin enhancements using FinFETs" 18 (18): 887-900, 2010
11 H. Qin, "SRAM leakage suppression by minimizing standby supply voltage" IEEE 55-60, 2004
12 H. Iwai, "Roadmap for 22 nm and beyond" 86 (86): 1520-1528, 2009
13 C. Zhao, "Review article advanced CMOS gate stack : present research progress" 2012 : 1-35, 2012
14 L. N. Liu, "Review : advances in la-based highk dielectrics for MOS applications" 9 (9): 1-30, 2019
15 S. J. Wang, "Reaction of SiO 2 with hafnium oxide in low oxygen pressure" 82 (82): 2047-2049, 2003
16 W. Lim, "Performance evaluation of 14 nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis" 2014 : 1-8, 2014
17 A.A. Kumar, "Performance analysis of 6T SRAM Cell on planar and FinFET technology" IEEE 0375-0379, 2019
18 Y. Li, "Numerical simulation of static noise margin for a six-transistor static random access memory cell with 32nm fi n-typed fi eld-eff ect transistors" Springer 227-234, 2007
19 J. P. Colinge, "Multiple-gate soi MOSFETs" 48 (48): 897-905, 2004
20 M.R. De Alba-Rosano, "Measuring leakage power in nanometer CMOS 6t-SRAM cells" IEEE 1-7, 2006
21 M. Mamidipaka, "Leakage power estimation in SRAMs" CECS 2003
22 J. C. Pravin, "Investigation of 6T SRAM memory circuit using high-k dielectrics based nanoscale junctionless transistor" 104 : 470-476, 2017
23 Gupta, M, "Impact of matched high-K gate dielectric based DG-MOSFET on SRAM performance. in 2017 4th International Conference on Power" 1-5, 2017
24 D. Schor, "IEDM 2017+ ISSCC 2018: Intel’s 10nm"
25 J. Dick, "IEDM 2016- setting the stage for 7/5nm from web site"
26 J. Robertson, "High dielectric constant oxides" 28 (28): 265-291, 2004
27 A. Kaur, "Hetero-dielectric oxide engineering on dopingless gate all around nanowire MOSFET with Schottky contact source/drain" 111 : 1-8, 2019
28 F. Ana, "Gate workfunction engineering for deep submicron MOSFET’s: motivation, features and challenges" 2 (2): 29-35, 2011
29 S. Khandelwal, "Finfet based 6t SRAM cell design: analysis of performance metric, process variation and temperature eff ect" 12 (12): 2500-2506, 2015
30 Z. Guo, "FinFET-based SRAM design" 2-7,
31 R. S. Kushwah, "FinFET-based 6T SRAM cell design:analysis of performance metric, process variation and temperature eff ect" 8 (8): 402-408, 2015
32 R. D. Clark, "Emerging applications for high k materials in VLSI technology" 7 (7): 2913-2944, 2014
33 K. Zhang, "Embedded Memories for Nano-Scale VLSIs (Vol.2)" Springer 2009
34 C. Zhao, "Dielectric relaxation of lanthanide-based ternary oxides : physical and mathematical models" 12 : 1-6, 2012
35 C. Z. Zhao, "Dielectric relaxation of la-doped zirconia caused by annealing ambient" 6 (6): 1-6, 2011
36 S. Saun, "Design and performance analysis of 6T SRAM cells on diff erent CMOS technologies with stability characterization" IOP Publishing 561 (561): 012093-, 2019
37 J. M. Gaskell, "Deposition of lanthanum zirconium oxide high-κ fi lms by liquid injection atomic layer deposition" 91 (91): 112912-, 2007
38 W. H. Strehlow, "Compilation of energy band gaps in elemental and binary compound semiconductors and insulators" 2 (2): 163-200, 1973
39 "Cogenda TCAD Tool Suite"
40 M. Limachia, "Characterization of various FinFET based 6T SRAM cell confi gurations in light of radiation eff ect" 45 (45): 31-, 2020
41 K. Nayak, "CMOS logic device and circuit performance of Si gate all around nanowire MOSFET" 61 (61): 3066-3074, 2014
42 M.G.C. de Andrade, "Behavior of triple-gate bulk FinFETs with and without DTMOS operation" 2011
43 X. Zhang, "Analysis of 7/8-nm bulk-Si FinFET technologies for 6T-SRAM scaling" 63 (63): 1502-1507, 2016
44 V. Sikarwar, "Analysis and design of low power SRAM cell using independent gate FinFET" 56 (56): 434-440, 2013
45 F. Chen, "A study of mixtures of HfO 2 and TiO 2 as high-k gate dielectrics" 72 : 263-266, 2004
Partial Discharge Activity Diagnosis in Electrical Cable Terminations Using Neural Networks
학술지 이력
연월일 | 이력구분 | 이력상세 | 등재구분 |
---|---|---|---|
2023 | 평가예정 | 해외DB학술지평가 신청대상 (해외등재 학술지 평가) | |
2020-01-01 | 평가 | 등재학술지 유지 (해외등재 학술지 평가) | |
2011-01-01 | 평가 | 등재학술지 유지 (등재유지) | |
2009-01-01 | 평가 | 등재학술지 유지 (등재유지) | |
2006-01-01 | 평가 | 등재학술지 선정 (등재후보2차) | |
2005-05-30 | 학회명변경 | 영문명 : 미등록 -> The Korean Institute of Electrical and Electronic Material Engineers | |
2005-05-30 | 학술지명변경 | 한글명 : Transactions on Electrical and Electroni -> Transactions on Electrical and Electronic Materials | |
2005-01-01 | 평가 | 등재후보 1차 PASS (등재후보1차) | |
2003-01-01 | 평가 | 등재후보학술지 선정 (신규평가) |
학술지 인용정보
기준연도 | WOS-KCI 통합IF(2년) | KCIF(2년) | KCIF(3년) |
---|---|---|---|
2016 | 0.08 | 0.08 | 0.1 |
KCIF(4년) | KCIF(5년) | 중심성지수(3년) | 즉시성지수 |
0.1 | 0.11 | 0.239 | 0.07 |