밀리미터파 대역 제2고조파 고효율 생성을 위한 부하 임피던스의 최적화 방법

다국어 초록 (Multilingual Abstract)

The objective of this paper is to present a quantitative analysis leading to the assessment of optimum terminating impedances in the design of active frequency multipliers. A brief analysis of the basic principal of the GaAs FET frequency multiplier is presented. The analysis is outlined in bias optimization and drive power determination. Utilizing the equivalent circuit model of GaAs FET, we have simulated the optimized load impedance for the maximum output of the active frequency multipliers. The C-class and reverse C-class frequency doublers have been fabricated and the load impedances have been measured. The experimental results are in good agreement with the estimated results in the simulation with the accuracy of 90%.

목차 (Table of Contents)

• Abstract
• 1. 서론
• 2. 체배동작의 원리
• 3. GaAs FET를 이용한 체배기
• 4. 실험 결과
• 5. 결론
• 참고문헌
• 저자소개

참고문헌 (Reference)

1 Califonia Eastern Laboratories, "Super Low Noise HJ FET"

2 G. T. Jr. Donald, "Single-ended HEMT multiplier design using reflector networks" 49 (49): 990-993, 2001

3 G. T. Jr. Donald, "Optimization of active microwave frequency multiplier performance utilizing harmonic terminating impedances" 44 (44): 2617-2624, 1996

4 M. Borg, "Novel MIC bipolar frequency doublers having high gain, wide bandwidth and good spectral performance" 39 (39): 1936-1946, 1991

5 Camargo, "Design of FET Frequency Multiplier and Harmonic Oscillators" Artech House 1998

6 Califonia Eastern Laboratories, "Converting GaAs FET Models for Different Nonlinear Simulators"

7 A. I. Melnnikov, "A specified model of the Schottky barrier diodes in the multipliers of frequency" 224-225, 2005

8 J. M. Putnam, "A high gain 18GHz single transistor frequency doubler" 372-373, 2002