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      KCI등재 SCIE SCOPUS

      Design of a High-performance High-pass Generalized Integrator Based Single-phase PLL

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      https://www.riss.kr/link?id=A103478092

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      다국어 초록 (Multilingual Abstract)

      Grid-interactive power converters are normally synchronized with the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and the d...

      Grid-interactive power converters are normally synchronized with the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and the dc offsets in single-phase systems. In this paper, a single-phase PLL is presented to mitigate the effects of these non-idealities. This PLL is based on the popular second order generalized integrator (SOGI) structure. The SOGI structure is modified to eliminate the effects of input dc offsets. The resulting SOGI structure has a high-pass filtering property. Hence, this PLL is termed as a high-pass generalized integrator based PLL (HGI-PLL). It has fixed parameters which reduces the implementation complexity and aids in the implementation in low-end digital controllers. The HGI-PLL is shown to have the lowest resource utilization among the SOGI based PLLs with dc cancelling capability. Systematic design methods are evolved leading to a design that limits the unit vector THD to within 1% for given non-ideal input conditions in terms of frequency deviation and harmonic distortion. The proposed designs achieve the fastest transient response. The performance of this PLL has been verified experimentally. The results agree with the theoretical prediction.

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      목차 (Table of Contents)

      • Abstract
      • I. INTRODUCTION
      • II. STRUCTURE AND DESIGN CONSIDERATIONS OF THE HGI-PLL
      • III. DESIGN OF THE HGI-PLL
      • IV. DESIGN SUMMARY
      • Abstract
      • I. INTRODUCTION
      • II. STRUCTURE AND DESIGN CONSIDERATIONS OF THE HGI-PLL
      • III. DESIGN OF THE HGI-PLL
      • IV. DESIGN SUMMARY
      • V. EXPERIMENTAL RESULTS
      • VI. CONCLUSIONS
      • REFERENCES
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      참고문헌 (Reference)

      1 C. Fitzer, "Voltage sag detection technique for a dynamic voltage restorer" 40 (40): 203-212, 2004

      2 A. Norouzi, "Two control schemes to enhance the dynamic performance of the STATCOM and SSSC" 20 (20): 435-442, 2005

      3 Y. Yang, "Synchronization in single-phase grid-connected photovoltaic systems under grid faults" 476-482, 2012

      4 A. Ghoshal, "Performance evaluation of three phase SRFPLL and MAF-SRF-PLL" 23 : 1781-1804, 2015

      5 V. Kaura, "Operation of a phase locked loop system under distorted utility conditions" 33 (33): 58-63, 1997

      6 M. Ciobotaru, "Offset rejection for pll based synchronization in grid-connected converters" 1611-1617, 2008

      7 P. Rodriguez, "New positive-sequence voltage detector for grid synchronization of power converters under faulty grid conditions" 1-7, 2006

      8 X. Zong, "New metric recommended for IEEE Std. 1547 to limit harmonics injected into distorted grids" 31 (31): 963-972, 2016

      9 K. Ogata, "Modern Control Engineering" Prentice Hall 2008

      10 M. Meral, "Improved phase-locked loop for robust and fast tracking of three phases under unbalanced electric grid conditions" 6 (6): 152-160, 2012

      1 C. Fitzer, "Voltage sag detection technique for a dynamic voltage restorer" 40 (40): 203-212, 2004

      2 A. Norouzi, "Two control schemes to enhance the dynamic performance of the STATCOM and SSSC" 20 (20): 435-442, 2005

      3 Y. Yang, "Synchronization in single-phase grid-connected photovoltaic systems under grid faults" 476-482, 2012

      4 A. Ghoshal, "Performance evaluation of three phase SRFPLL and MAF-SRF-PLL" 23 : 1781-1804, 2015

      5 V. Kaura, "Operation of a phase locked loop system under distorted utility conditions" 33 (33): 58-63, 1997

      6 M. Ciobotaru, "Offset rejection for pll based synchronization in grid-connected converters" 1611-1617, 2008

      7 P. Rodriguez, "New positive-sequence voltage detector for grid synchronization of power converters under faulty grid conditions" 1-7, 2006

      8 X. Zong, "New metric recommended for IEEE Std. 1547 to limit harmonics injected into distorted grids" 31 (31): 963-972, 2016

      9 K. Ogata, "Modern Control Engineering" Prentice Hall 2008

      10 M. Meral, "Improved phase-locked loop for robust and fast tracking of three phases under unbalanced electric grid conditions" 6 (6): 152-160, 2012

      11 B. Singh, "Implementation of single-phase enhanced phase-locked loop-based control algorithm for three-phase DSTATCOM" 28 (28): 1516-1524, 2013

      12 "IEEE standard for interconnecting distributed resources with electric power systems"

      13 "IEEE recommended practices and requirements for harmonic control in electrical power systems"

      14 "IEEE recommended practice for monitoring electric power quality"

      15 A. Luna, "Grid voltage synchronization for distributed generation systems under grid fault conditions" 51 (51): 3414-3425, 2015

      16 Y. F. Wang, "Grid synchronization PLL based on cascaded delayed signal cancellation" 26 (26): 1987-1997, 2011

      17 R. Teodorescu, "Flexible control of small wind turbines with grid failure detection operating in stand-alone and grid-connected mode" 19 (19): 1323-1332, 2004

      18 A. Timbus, "Evaluation of current controllers for distributed power generation systems" 24 (24): 654-664, 2009

      19 A. Kulkarni, "Design of synchronous reference frame phase-locked loop with the presence of dc offsets in the input voltage" 8 (8): 2435-2443, 2015

      20 H. Tao, "Control of grid-interactive inverters as used in small distributed generators" 1574-1581, 2007

      21 Z. Wang, "Control of a six-switch inverter based single-phase grid-connected PV generation system with inverse park transform PLL" 258-263, 2012

      22 K. Nagaraj, "Architectures and circuit techniques for multi-purpose digital phase lock loops" 60 (60): 517-528, 2013

      23 A. Kulkarni, "Analysis of bandwidth-unit-vector-distortion tradeoff in PLL during abnormal grid conditions" 60 (60): 5820-5829, 2013

      24 J. Matas, "An adaptive pre-filtering method to improve the speed/accuracy tradeoff of voltage sequence detection methods under adverse grid conditions" 61 (61): 2139-2151, 2014

      25 R. Menzies, "Advances in the determination of control parameters for static compensators" 4 (4): 2012-2017, 1989

      26 M. Reza, "Accurate estimation of single-phase grid voltage parameters under distorted conditions" 29 (29): 1138-1146, 2014

      27 S. Shinnaka, "A robust single-phase pll system with stable and fast tracking" 44 (44): 624-633, 2008

      28 M. Karimi-Ghartemani, "A novel three-phase magnitude-phase-locked loop system" 53 (53): 1792-1802, 2006

      29 A. Kulkarni, "A novel design method for SOGI-PLL for minimum settling time and low unit vector distortion" 274-279, 2013

      30 M. Ciobotaru, "A new single-phase pll structure based on second order generalized integrator" 1-6, 2006

      31 G. Buticchi, "A dc offset current compensation strategy in transformerless grid-connected power converters" 26 (26): 2743-2751, 2011

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2014-10-08 학술지명변경 한글명 : 전력전자학회 영문논문지 -> Journal of Power Electronics KCI등재
      2010-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2007-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2006-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2004-07-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

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      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.83 0.54 0.74
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.65 0.62 0.382 0.06
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