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https://www.riss.kr/link?id=O36534625
2000년
eng
1552-6674
2471-7827
학술저널
IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP
15-20 [※수록면이 p5 이하이면, Review, Columns, Editor's Note, Abstract 등일 경우가 있습니다.]
0769507867
IEEE international high-level design validation and test workshop
5th
Berkeley, CA
2000; Nov
0
상세조회0
다운로드
An RT-Level Fault Model with High Gate Level Correlation
A Novel Methodology for Hierarchical Test Generation Using Functional Constraint Composition
Behavioral-Level Test Vector Generation for System-on-Chip Designs
An Approach to Functional Testing of VLIW Architectures