고장위치 및 검사신호의 병렬화에 의한 고장 모의실험 = A Fault Simulation Method by Parallelizing Faults and Patterns

다국어 초록 (Multilingual Abstract)

The two different fault simulation methods for the combinational circuits have been interested during the recent years. One method parallelizes the faults and the other parallelizes the test patterns for the effective fault simulation. The two methods have defferent attractive features for their own properties. In this paper, each attractive benefit is adopted for the improvement of performance with the proposed fault simulation method. In the Proposed algorithm, the both parallelizing methods are used. The method of parallelizing faults is used for the detection of the reconvergent stem fault. The method of parallelizing test patterns is used for the detection of the other faults. To illustrate the performance of the proposed algorithm, two different methods are compared with the proposed one in the several benchmark circuits. The experimental result shows that the proposed method achieves better performance about 1.8 times than the two parallelizing methods.