An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With <tex> $0.175~\mu$</tex>W/Channel in 65-nm CMOS

다국어 초록 (Multilingual Abstract)

<P>This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller area per channel. Time-multiplexed registers are utilized in the detector for dynamic power reduction. Finally, an ultralow-voltage 8T static random access memory (SRAM) is developed to reduce area and leakage consumption when compared to D flip-flop -based memory. The proposed SSP, fabricated in 65-nm CMOS process technology, consumes only 0.175 <TEX>$\mu \text{W}$</TEX>/channel when processing 128 input channels at 3.2 MHz and 0.54 V, which is the lowest among the compared state-of-the-art SSPs. The proposed SSP also occupies 0.003 mm<SUP>2</SUP>/channel, which allows 333 channels/mm<SUP>2</SUP>.</P>