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      KCI등재 SCIE SCOPUS

      Processing and Characterization of Ultra-thin Poly-crystalline Silicon for Memory and Logic Applications

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      https://www.riss.kr/link?id=A105293716

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      다국어 초록 (Multilingual Abstract)

      In this work, processing and characterization of ultra-thin poly-Si are performed for memory and logic applications. Ultra-thin poly-Si layers with different thicknesses were prepared on the deposited oxide by low-pressure chemical vapor deposition (L...

      In this work, processing and characterization of ultra-thin poly-Si are performed for memory and logic applications. Ultra-thin poly-Si layers with different thicknesses were prepared on the deposited oxide by low-pressure chemical vapor deposition (LPCVD). Deposited poly-Si were doped through POCl3 gas-phase doping at 900 °C, in which 10-nm thickness was reduced. Afterward, postdeposition annealing (PDA) under different conditions were performed. Thicknesses of deposited poly-Si films were 20, 30, and 50 nm. The following PDA improves the crystallinity, which has been confirmed by high-resolution transmission electron
      microscopy (HR-TEM) with fast Fourier transform (FFT) imaging and sheet resistivity lowering. Also, superior crystalline film is observed in the thinner film and the bi-directionally arranged domains are obtained from the 40-nm poly-Si film.

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      목차 (Table of Contents)

      • Abstract
      • I. INTRODUCTION
      • II. EXPERIMENTAL
      • III. RESULTS AND DISCUSSION
      • IV. CONCLUSION
      • Abstract
      • I. INTRODUCTION
      • II. EXPERIMENTAL
      • III. RESULTS AND DISCUSSION
      • IV. CONCLUSION
      • REFERENCES
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      참고문헌 (Reference)

      1 J. Jang, "Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory" 192-193, 2009

      2 L. Chen, "Vertical Ge/Si core/shell nanowire junctionless transistor" 16 (16): 420-426, 2016

      3 A. M. Lonescu, "Tunnel field-effect transistors as energy-efficient electronic switches" 479 : 329-337, 2011

      4 W. Zhang, "The ITFET: A Novel FinFET-Based Hybrid Device" 53 (53): 2335-2343, 2006

      5 Young Jun Yoon, "Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications" 대한전자공학회 16 (16): 172-178, 2016

      6 J.-G. Yun, "Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application" 64 (64): 42-46, 2011

      7 S. Cho, "Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation" 99 (99): 243505-, 2011

      8 S. Cho, "Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation" 99 (99): 243505-, 2011

      9 H. Kim, "Silicon-Based Floating-Body Synaptic Transistor With Frequency-Dependent Short- and Long-Term Memories" 37 (37): 249-252, 2016

      10 S. Cho, "RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs" 58 (58): 1388-1396, 2011

      1 J. Jang, "Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory" 192-193, 2009

      2 L. Chen, "Vertical Ge/Si core/shell nanowire junctionless transistor" 16 (16): 420-426, 2016

      3 A. M. Lonescu, "Tunnel field-effect transistors as energy-efficient electronic switches" 479 : 329-337, 2011

      4 W. Zhang, "The ITFET: A Novel FinFET-Based Hybrid Device" 53 (53): 2335-2343, 2006

      5 Young Jun Yoon, "Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications" 대한전자공학회 16 (16): 172-178, 2016

      6 J.-G. Yun, "Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application" 64 (64): 42-46, 2011

      7 S. Cho, "Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation" 99 (99): 243505-, 2011

      8 S. Cho, "Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation" 99 (99): 243505-, 2011

      9 H. Kim, "Silicon-Based Floating-Body Synaptic Transistor With Frequency-Dependent Short- and Long-Term Memories" 37 (37): 249-252, 2016

      10 S. Cho, "RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs" 58 (58): 1388-1396, 2011

      11 R. Katsumata, "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices" 136-137, 2009

      12 Y. Fukuzumi, "Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory" 449-452, 2007

      13 S. Whang, "Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application" 29.7.1-29.7.1.4, 2010

      14 W. Kim, "Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage" 188-189, 2009

      15 C. Kittel, "Introduction to Solid State Physics" John Wiley & Sons 2004

      16 M.-H. Baek, "Hole Trapping Phenomenon at the Grain Boundary of Thin Poly-Si Floating-Body MOSFET and Its Capacitor-Less DRAM Application" 17 (17): 2986-2990, 2017

      17 김영민, "High-Speed Low-Power Junctionless Field-Effect Transistor with Ultra-Thin Poly-Si Channel for Sub-10-nm Technology Node" 대한전자공학회 16 (16): 159-165, 2016

      18 W. S. Yoo, "Grain size monitoring of 3D flash memory channel poly-Si using multiwavelength Raman spectroscopy" 1-4, 2014

      19 J. G. Fossum, "Effects of grain boundaries on the channel conductance of SOl MOSFET's" 30 (30): 933-940, 1983

      20 C. Herring, "Diffusional Viscosity of a Polycrystalline Solid" 21 (21): 437-445, 1950

      21 J. Lee, "Design of Poly-Si Junctionless Fin-Channel FET With Quantum-Mechanical Drift-Diffusion Models for Sub-10-nm Technology Nodes" 63 (63): 4610-4616, 2016

      22 E. Yu, "Design and analysis of nanowire p-type MOSFET coaxially having silicon core and germanium peripheral channel" 55 (55): 114001-, 2016

      23 S. Nakaharai, "Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge condensation technique" 83 (83): 3516-3518, 2003

      24 S. D. Suk, "Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure" 142-143, 2009

      25 Y. T. Chen, "Capacitorless 1T Memory Cells Using Channel Traps at Grain Boundaries" 31 (31): 1125-1127, 2010

      26 N. Weste, "CMOS VLSI Design: A Circuit and Systems Perspective" Addison Wesley 2010

      27 H. Aochi, "BiCS Flash as a Future 3D Non-Volatile Memory Technology for Ultra High Density Storage Devices" 1-2, 2009

      28 S. Cho, "Analyses on Small-Signal Parameters and Radio Frequency Modeling of Gate-All-Around Tunneling Field-Effect Transistors" 58 (58): 4164-4171, 2011

      29 S. J. Choi, "A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory" 111-112, 2010

      30 H.-T. Lue, "A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device" 131-132, 2010

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      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2014-01-21 학회명변경 영문명 : The Institute Of Electronics Engineers Of Korea -> The Institute of Electronics and Information Engineers KCI등재
      2010-11-25 학술지명변경 한글명 : JOURNAL OF SEMICONDUTOR TECHNOLOGY AND SCIENCE -> JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE KCI등재
      2010-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2009-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2007-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.42 0.13 0.35
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.3 0.29 0.308 0.03
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