A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch

다국어 초록 (Multilingual Abstract)

This work proposes a two-channel T-I 10b 160 MS/s asynchronous pipelined-SAR ADC minimizing offset and gain mismatches between channels without any calibration. Each channel of the proposed ADC is based on a two-stage pipelined-SAR topology, where the first and second stage determines 4b and 7b, respectively, for high conversion rate and low power. An asynchronous SAR algorithm removes on-chip high-speed clock generators for SAR operation, while a simple detection circuit solves a meta-stability problem of the comparator commonly observed in asynchronous SAR ADCs. Analog circuits such as comparators and residue amplifiers are shared to capacity between two channels to reduce various channel mismatches limiting the linearity of the T-I ADC. Three separate reference voltage drivers for two SAR ADCs and a residue amplifier prevent lots of undesirable disturbance among reference voltages due to each different switching operation. The prototype ADC in a 28 nm CMOS process demonstrates a measured differential and integral non-linearity within 0.71 LSB and 0.70 LSB at 10b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 51.43 dB and 62.01 dB at 160 MS/s, respectively. The proposed ADC occupies an active die area of $0.23mm^2$ and consumes 3.5 mW at a 1.0 V supply voltage.