A voltage reference having a maximum TC of-0.45%/℃ is presented. The proposed scheme comprises a MOS bandgap voltage reference, a PTAT voltage reference and a voltage subtractor. This circuit is designed using a 0.18-㎛ CMOS process, whose size is ...
A voltage reference having a maximum TC of-0.45%/℃ is presented. The proposed scheme comprises a MOS bandgap voltage reference, a PTAT voltage reference and a voltage subtractor. This circuit is designed using a 0.18-㎛ CMOS process, whose size is 450㎛×400㎛ and power consumption is 12.3㎼ at room temperature. The proposed scheme improves immunity to both process and resistor variation by 4 times of the conventional scheme (±20% → ±5%).