1 "플래시메모리를 위한 Scaled SONOSFET NVSM 의 프로그래밍 조건과 특성에 관한 연구" 13 (13): 914-, 2000.
2 "Partial Response Detection Technique for Driver Power Reduction in High-speed Memory - to - Processor Communications" 342-, 1997.
3 "Digital delay locked loop and design technique for high-speed synchronous interface" E79-C (E79-C): 798-, June1996.
4 "All-digital multiphase delay locked loop for internal timing generation in embedded and/or high-speed DRAMs." 107-, 1997.
5 "A study on sol-like-bulk CMOS structure operationg in low voltage with stability" 11 (11): 1998.
6 "A Portable Digital DLL Architecture for CMOS Interface Circuit" 1998.
7 "A 2.5-ns clock access, 250MHz, 256Mb SDRAM with synchronous mirror delay" 31 : 1656-, 1996.
8 "6H-SiC MOSFET과 디지털 IC 제작" 16 (16): 584-, 2003.
1 "플래시메모리를 위한 Scaled SONOSFET NVSM 의 프로그래밍 조건과 특성에 관한 연구" 13 (13): 914-, 2000.
2 "Partial Response Detection Technique for Driver Power Reduction in High-speed Memory - to - Processor Communications" 342-, 1997.
3 "Digital delay locked loop and design technique for high-speed synchronous interface" E79-C (E79-C): 798-, June1996.
4 "All-digital multiphase delay locked loop for internal timing generation in embedded and/or high-speed DRAMs." 107-, 1997.
5 "A study on sol-like-bulk CMOS structure operationg in low voltage with stability" 11 (11): 1998.
6 "A Portable Digital DLL Architecture for CMOS Interface Circuit" 1998.
7 "A 2.5-ns clock access, 250MHz, 256Mb SDRAM with synchronous mirror delay" 31 : 1656-, 1996.
8 "6H-SiC MOSFET과 디지털 IC 제작" 16 (16): 584-, 2003.