A CMOS vector summation circuit using the square-law characteristic of MOS transistors in saturation is presented. This circuit is widely used in communication, in order to analyze and processing the signal. The previous papers proposed to use the tra...
A CMOS vector summation circuit using the square-law characteristic of MOS transistors in saturation is presented. This circuit is widely used in communication, in order to analyze and processing the signal. The previous papers proposed to use the translinear of bipolar transistor, operational amplifier or current conveyor. The paper proposes to design the vector summation circuit by using MOS transistors and suitable for integrated circuit.