Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs

다국어 초록 (Multilingual Abstract)

To reduce interconnect delay and power consumptionwhile improving chip performance, a three-dimensionalintegrated circuit (3D IC) has been developed with diestackingand through-silicon via (TSV) techniques. Thepower supply problem is one of the essential challenges in3D IC design because IR-drop caused by insufficientsupply voltage in a 3D chip reduces the chip performance.
In particular, power bumps and TSVs are placed tominimize IR-drop in a 3D power delivery network. In thispaper, we propose a design methodology for 3D powerdelivery networks to minimize the number of powerbumps and TSVs with optimum mesh structure anddistribute voltage variation more uniformly by shifting thelocations of power bumps and TSVs while satisfying IRdropconstraint. Simulation results show that our methodcan reduce the voltage variation by 29.7% on averagewhile reducing the number of power bumps and TSVs by76.2% and 15.4%, respectively.

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