We propose a 6 bits 10 MS/s asynchronous loop-unrolled (LU) successive approximation register (SAR) analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs). The proposed LU SAR ADC performs comparison operations using both the r...
We propose a 6 bits 10 MS/s asynchronous loop-unrolled (LU) successive approximation register (SAR) analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs). The proposed LU SAR ADC performs comparison operations using both the rising and falling edges of the clock by utilizing CDA. This reduces power consumption of the comparator and clock generator, and halves the number of comparators, thus enhancing the power and area efficiencies. Designed using a 500nm CMOS process, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at 4.77MHz input are 37.8 and 46.5 dB, respectively.