This paper suggests a cache coherence protocol which improves the efficiency of MESI protocol.
The suggested cache coherence protocol maintains 6 types of cache states and ID area. The cache states are divided into 3 valid (exclusive, modified, modi...
This paper suggests a cache coherence protocol which improves the efficiency of MESI protocol.
The suggested cache coherence protocol maintains 6 types of cache states and ID area. The cache states are divided into 3 valid (exclusive, modified, modified-shared, shared) and 2 invalid (invalid, invalid-by-other) states. ID area holds the identification of the processor module with valid block. We can decrease broadcasting and snooping by the suggested protocol. In addition to it, we can shorten the responce time through cache-to-cache communication.
According to simulation results, We get around 2% efficiency improvement compared with MMESSII protocol which is a improved MESI protocol as the number of processors are increasing.