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あぁかがさざただなはばぱまやゃらわゎんいぃきぎしじちぢにひびぴみりうぅくぐすずつづっぬふぶぷむゆゅるえぇけげせぜてでねへべぺめれおぉこごそぞとどのほぼぽもよょろを

アァカサザタダナハバパマヤャラワヮンイィキギシジチヂニヒビピミリウゥクグスズツヅッヌフブプムユュルエェケゲセゼテデヘベペメレオォコゴソゾトドノホボポモヨョロヲ ―

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中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
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Α Β Γ Δ Ε Ζ Η Θ Ι Κ Λ Μ Ν Ξ Ο Π Ρ Σ Τ Υ Φ Χ Ψ Ω α β γ δ ε ζ η θ ι κ λ μ ν ξ ο π ρ σ τ υ φ χ ψ ω

á à Á À é è É È ç Ç ê

Ä Ö Ü ä ö ü ß

ְ ֳ ֲ ֱ ָ ַ ֵ ֶ ִ ֹ ּ ֻ ׂ ׁ ּ פ ם ן ו ט א ר ק ף ך ל ח י ע כ ג ד ש ץ ת צ מ נ ה ב

‘ ’ “ ” 〔〕〈〉「」『』【】＂（）［］｛｝

± × ÷ ≠ ≤ ≥ ∞ ∴ ♂ ♀ ∠ ⊥ ⌒ ∂ ∇ ≡ ≒ ≪ ≫ √ ∽ ∝ ∵ ∫ ∬ ∈ ∋ ⊆ ⊇ ⊂ ⊃ ∪ ∩ ∧ ∨ ￢ ⇒ ⇔ ∀ ∃ ∮ ∑ ∏ ＋－＜＝＞

、。 · ‥ … ¨ 〃 ― ∥ ＼ ∼ ´ ～ ˇ ˘ ˝ ˚ ˙ ¸ ˛ ¡ ¿ ː ！＇，．／：；？＾＿｀｜

½ ⅓ ⅔ ¼ ¾ ⅛ ⅜ ⅝ ⅞ ¹ ² ³ ⁴ ⁿ ₁ ₂ ₃ ₄

Æ Ð Ħ Ĳ Ł Ø Œ Þ Ŧ Ŋ æ đ ð ħ ı ĳ ĸ ŀ ł ø œ ß þ ŧ ŋ ŉ

А Б В Г Д Е Ё Ж З И Й К Л М Н О П Р С Т У Ф Х Ц Ч Ш Щ Ъ Ы Ь Э Ю Я а б в г д е ё ж з и й к л м н о п р с т у ф х ц ч ш щ ъ ы ь э ю я

′ ″ ℃ Å ￠￡￥ ¤ ℉ ‰ ＄％Ｆ￦㎕㎖㎗ ℓ ㎘㏄㎣㎤㎥㎦㎙㎚㎛㎜㎝㎞㎟㎠㎡㎢㏊㎍㎎㎏㏏㎈㎉㏈㎧㎨㎰㎱㎲㎳㎴㎵㎶㎷㎸㎹㎀㎁㎂㎃㎄㎺㎻㎽㎾㎿㎐㎑㎒㎓㎔ Ω ㏀㏁㎊㎋㎌㏖㏅㎭㎮㎯㏛㎩㎪㎫㎬㏝㏐㏓㏃㏉㏜㏆

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ا ب ت ث ج ح خ د ذ ر ز س ش ص ض ط ظ ع غ ف ق ک ل م ن ه و ی

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RISS 인기검색어

저전압 고속 전류형 Pipelined A/D 변환기의 설계 = Design of A Low-Voltage and High-Speed Pipelined A/D Converter Using Current-Mode Signals

한글로보기

https://www.riss.kr/link?id=A106789618

저자

박승균 ; 이희덕 ; 한철희
발행기관
대한전자공학회
학술지명
전자공학회논문지A
권호사항

Vol.31 No.3 [1994]
발행연도
1994
작성언어
Korean
자료형태
학술저널
발행기관 URL
http://www.ieek.or.kr
수록면

18-27(10쪽)
제공처
ScienceON

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다국어 초록 (Multilingual Abstract)

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.

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An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D con...

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.