1 J. Kang, "Way-tracking set-associative caches" 46 (46): 1497-1499, 2010
2 K. Inoue, "Way-predicting set-associative cache for high performance and low energy consumption" 273-275, 1999
3 S. Lee, "Way-lookup buffer for low-power set-associative cache" 8 (8): 1961-1966, 2011
4 D. Brooks, "Wattch: a framework for architectural-level power analysis and optimizations" 83-94, 2000
5 D. Burger, "The simplescalar tool set version 2.0" University of Wisconsin 1997
6 "SPEC 2000 Benchmark"
7 A. Hasegawa, "SH3: high code density, low power" 11-19, 1999
8 D. Nicolaescu, "Reducing power consumption for high-associativity data caches in embedded processors" 1064-1068, 2003
9 D. A. Patterson, "Computer architecture: a quantitative approach" Morgan Kaufmann Publishers 2002
10 N. Muralimanohar, "CACTI 6.0: A tool to model large caches" HP Laboratories 2009
1 J. Kang, "Way-tracking set-associative caches" 46 (46): 1497-1499, 2010
2 K. Inoue, "Way-predicting set-associative cache for high performance and low energy consumption" 273-275, 1999
3 S. Lee, "Way-lookup buffer for low-power set-associative cache" 8 (8): 1961-1966, 2011
4 D. Brooks, "Wattch: a framework for architectural-level power analysis and optimizations" 83-94, 2000
5 D. Burger, "The simplescalar tool set version 2.0" University of Wisconsin 1997
6 "SPEC 2000 Benchmark"
7 A. Hasegawa, "SH3: high code density, low power" 11-19, 1999
8 D. Nicolaescu, "Reducing power consumption for high-associativity data caches in embedded processors" 1064-1068, 2003
9 D. A. Patterson, "Computer architecture: a quantitative approach" Morgan Kaufmann Publishers 2002
10 N. Muralimanohar, "CACTI 6.0: A tool to model large caches" HP Laboratories 2009
11 J. Montanaro, "A 160 MHz, 32b 0.5W CMOS RISC microprocessor" 31 (31): 1703-1714, 1996