1 M. Abramovici, "Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications" 973-982, 1999
2 Sony Corporation, "Sony Semiconductor Quality and Reliability Handbook"
3 "Renesas Electronics, Semiconductor Reliability Handbook, Rev.1.01"
4 박영규, "IEEE 1500 표준 기반의 효율적인 프로그램 가능한 메모리 BIST" 대한전자공학회 50 (50): 114-121, 2013
5 "IEEE 1149.1 JTAG Boundary-Scan Testing in Altera Devices"
6 P. Gadde, "FPGA Memory Testing Technique using BIST" 473-476, 2013
7 K. Ito, "Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test" 113 (113): 1-6, 2013
8 N. Das, "Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate array" 7 (7): 210-220, 2013
9 S. Vemula, "Built-in self-test for programmable I/O buffers in FPGAs and SoCs" 534-538, 2006
10 C. Hsu, "Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA" 58 (58): 2300-2315, 2009
1 M. Abramovici, "Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications" 973-982, 1999
2 Sony Corporation, "Sony Semiconductor Quality and Reliability Handbook"
3 "Renesas Electronics, Semiconductor Reliability Handbook, Rev.1.01"
4 박영규, "IEEE 1500 표준 기반의 효율적인 프로그램 가능한 메모리 BIST" 대한전자공학회 50 (50): 114-121, 2013
5 "IEEE 1149.1 JTAG Boundary-Scan Testing in Altera Devices"
6 P. Gadde, "FPGA Memory Testing Technique using BIST" 473-476, 2013
7 K. Ito, "Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test" 113 (113): 1-6, 2013
8 N. Das, "Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate array" 7 (7): 210-220, 2013
9 S. Vemula, "Built-in self-test for programmable I/O buffers in FPGAs and SoCs" 534-538, 2006
10 C. Hsu, "Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA" 58 (58): 2300-2315, 2009
11 Y. Kim, "BIST structure based on new Random Access Scan architecture for Low Power Scan Test" 812-815, 2009
12 S. Rehman, "BIST for Logic and Local Interconnect Resources in a Novel Mesh of Cluster FPGA" 296-301, 2013