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      KCI등재 SCIE SCOPUS

      Flexible WOM Codes for NAND Flash Memory Based on Raptor-Like Codes

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      https://www.riss.kr/link?id=A106038547

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      다국어 초록 (Multilingual Abstract)

      Write-once memory (WOM) codes aim to extend the lifetimeand improve the writing efficiency of storage devices such asNAND flash memory by reducing the number of erase operations. In this paper, a new rewriting scheme for NAND flash memory isproposed, ...

      Write-once memory (WOM) codes aim to extend the lifetimeand improve the writing efficiency of storage devices such asNAND flash memory by reducing the number of erase operations.
      In this paper, a new rewriting scheme for NAND flash memory isproposed, which supports two writes (or only one rewrite) and allowsthe second write incrementally done multiple times by usingraptor-like codes as rate-compatible (RC) low-density generatormatrix (LDGM) codes. The proposed scheme improves writing efficiencyof the NAND flash memory when combined with a properpage selection method. It is verified via numerical analysis that theproposedWOM codes outperform the conventionalWOM codes interms of writing efficiency.

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      참고문헌 (Reference)

      1 G. Yadgar, "Write once, get 50% free: Saving SSD erase costs using WOM codes" 257-271, 2015

      2 A. Jagmohan, "Write amplification reduction in NAND flash through multi-write coding" 1-6, 2010

      3 H. Choi, "VLSI implementation of BCH error correction for multilevel cell NAND flash memory" 18 (18): 843-847, 2010

      4 F. Margaglia, "The devil is in the details: Implementing flash page reuse with WOM codes" 95-109, 2016

      5 T. Nguyen, "The design of rate-compatible protograph LDPC codes" 60 (60): 2841-2850, 2012

      6 E. E. Gad, "Rewriting flash memories by message passing" 646-650, 2015

      7 E. Yaakobi, "Rewriting codes for flash memories" 60 (60): 964-975, 2014

      8 T. V. Nguyen, "Rate-compatible short-length protograph LDPC codes" 17 (17): 948-951, 2013

      9 J. Kim, "Rate-0.96 LDPC decoding VLSI for soft-decision error correction of NAND flash memory" 22 (22): 1004-1015, 2014

      10 T.-Y. Chen, "Protograph-based raptor-like LDPC codes" 63 (63): 1522-1532, 2015

      1 G. Yadgar, "Write once, get 50% free: Saving SSD erase costs using WOM codes" 257-271, 2015

      2 A. Jagmohan, "Write amplification reduction in NAND flash through multi-write coding" 1-6, 2010

      3 H. Choi, "VLSI implementation of BCH error correction for multilevel cell NAND flash memory" 18 (18): 843-847, 2010

      4 F. Margaglia, "The devil is in the details: Implementing flash page reuse with WOM codes" 95-109, 2016

      5 T. Nguyen, "The design of rate-compatible protograph LDPC codes" 60 (60): 2841-2850, 2012

      6 E. E. Gad, "Rewriting flash memories by message passing" 646-650, 2015

      7 E. Yaakobi, "Rewriting codes for flash memories" 60 (60): 964-975, 2014

      8 T. V. Nguyen, "Rate-compatible short-length protograph LDPC codes" 17 (17): 948-951, 2013

      9 J. Kim, "Rate-0.96 LDPC decoding VLSI for soft-decision error correction of NAND flash memory" 22 (22): 1004-1015, 2014

      10 T.-Y. Chen, "Protograph-based raptor-like LDPC codes" 63 (63): 1522-1532, 2015

      11 D. Divsalar, "Protograph based LDPC codes with minimum distance linearly growing with block size" 1152-1156, 2005

      12 G. Liva, "Protograph LDPC code design based on EXIT chart analysis" 3250-3254, 2007

      13 D. Burshtein, "Polar write once memory codes" 59 (59): 5088-5101, 2013

      14 C. Heegard, "On the capacity of permanent memory" 31 (31): 34-42, 1985

      15 J. Thorpe, "Low-density parity-check (LDPC) codes constructed from protographs" 1-7, 2003

      16 E. Martinian, "Iterative quantization using codes on graphs" 2003

      17 F. Margaglia, "Improving MLC flash performance and endurance with extended P/E cycles" 1-12, 2015

      18 R. L. Rivest, "How to reuse a write-once memory" 55 (55): 1-19, 1982

      19 W. J. M. Chua, "Efficient two-write WOMcodes for non-volatile memories" 19 (19): 1690-1693, 2015

      20 L. M. Grupp, "Characterizing flash memory: Anomalies, observations, and applications" 24-33, 2009

      21 D. Divsalar, "Capacityapproaching protograph codes" 27 (27): 876-888, 2009

      22 R. Sekiya, "Applying write-once memory codes to binary symmetric asymmetric multiple access channels" E99-A (E99-A): 2202-2210, 2016

      23 S. Kotaki, "An error correction method for neighborhood-level errors in NAND flash memories" E100-A (E100-A): 653-662, 2017

      24 T.-S. Chung, "A survey of flash translation layer" 55 : 332-343, 2009

      25 S. Tanakamaru, "A design strategy of errorprediction low-density parity-check (EP-LDPC) error-correcting code (ECC) and error-recovery schemes for scaled NAND flash memories" E98-C (E98-C): 53-61, 2015

      26 Z. Li, "A class of good quasi-cyclic low-density parity check codes based on progressive edge growth graph" 1990-1994, 2004

      27 Lin Zhou, "A Non-Greedy Puncturing Method for Rate-Compatible LDPC Codes" 한국통신학회 19 (19): 32-40, 2017

      28 Sunghoon Choi, "A Good Puncturing Scheme for Rate Compatible Low-Density Parity-Check Codes" 한국통신학회 11 (11): 455-463, 2009

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2005-01-01 평가 SCI 등재 (등재후보1차) KCI등재
      2004-01-01 평가 등재후보학술지 유지 (등재후보2차) KCI등재후보
      2003-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2001-07-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.74 0.09 0.53
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.42 0.34 0.264 0.02
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