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Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank
Lewis, M.;Brackenbury, L. IEEE Computer Society 2001 p.4-14
A Low-Power Self-Timed Viterbi Decoder
Riocreux, P.;Brackenbury, L.;Cumpstey, M.;Furber, S. IEEE Computer Society 2001 p.15-24
A Multi-Radix Approach to Asynchronous Division
Cornetta, G.;Cortadella, J. IEEE Computer Society 2001 p.25-35
A Practical Comparison of Asynchronous Design Styles
Lloyd, D.;Garside, J. IEEE Computer Society 2001 p.36-45
Sutherland, I.;Fairbanks, S. IEEE Computer Society 2001 p.46-53
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI
Konishi, R.;Ito, H.;Nakada, H.;Nagoya, A.;Oguri, K.;Imlig, N.;Shiozawa, T.;Inamori, M.;Nagami, K. IEEE Computer Society 2001 p.54-63
Efficient Exact Two-Level Hazard-Free Logic Minimization
Myers, C.;Jacobson, H. IEEE Computer Society 2001 p.64-73
Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits
Berks, R.;Negulescu, R. IEEE Computer Society 2001 p.74-85
Synchronous Handshake Circuits
Peeters, A.;van Berkel, K. IEEE Computer Society 2001 p.86-95