FPGA를 이용한 영상처리 보드 설계 및 알고리즘 구현

다국어 초록 (Multilingual Abstract)

FPGA-based Board that is compatible with DSK Board for image processing systems was designed and implemented. This board was used as pre-processing with a video data.
OS filter and edge detection algorithms were applied to FPGA-based Board. OS filter is used to pipelined structure, which provides fast processing speed. and edge detection algorithm is implemented with Multiplier-less and reduced number of Adder structure. This Algorithm can reduce computational complexity.
The FPGA-based Board can process 30 frames per 1 second, and VGA resolution of 640×480 was implemented.

목차 (Table of Contents)

• 제 1 장 서 론 1
• 제 2 장 NTSC 3
• 2.1 비월주사 방식 3
• 2.2 순차주사 방식 4
• 2.3 NTSC의 색 신호 5
• 2.4 ITU-R BT.601 6
• 제 3 장 하드웨어 시스템 9
• 3.1 FPGA Board의 구성 9
• 3.2 Video Decoder 11
• 3.2.1 I2C 12
• 3.2.2 Interface Mode 13
• 3.3 Video Encoder 15
• 제 4 장 FPGA 구현 17
• 4.1 FPGA 내부 구성 17
• 4.1.1 ITU-R BT.656 디코더 19
• 4.1.2 YCbCr to RGB 19
• 4.1.3 VGA Timing 20
• 4.1.4 Line Buffer 21
• 4.2 OS Filter의 구현 23
• 4.3 윤곽선 검출 28
• 4.3.1 Sobel Edge Filter 28
• 4.3.2 DPF 30
• 제 5 장 결론 및 고찰 40
• 참고문헌 41