CPLD 소자를 사용한 DDS 방식의 고속 주파수 호핑용 디지털 주파수 합성기의 설계 = Design of the Digital Frequency Synthesizer for High Speed Frequency Hopping by the DDS Method using CPLD

국문 초록 (Abstract)

주파수 합성기로서 통신시스템에 많이 사용되어온 PLL 방식은 여러 장점을 갖고 있지만, 위상잡음 특성이 나쁘고 주파수 도약 시간이 긴 단점을 갖기 때문에 최근의 고속(l$mu$s이하)으로 주파수 호핑(Frequency Hopping)을 요구하는 차세대 이동 통신 시스템에서는 사용이 불가능하다. 본 연구는 차세대 이동통신 시스템에서 1600 hops/s 속도로 600개 이상의 랜덤한 주파수를 발생하는 주파수합성기를 CPLD를 사용하여 DDS (Direct Digital Synthesis) 방식으로 설계하였다.

다국어 초록 (Multilingual Abstract)

The PLL synthesizer is used in communication system until now because it have several merits, such as broad bandwidth, high accuracy and stability of frequency But it is difficult to use in the third generation mobile communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed the frequency synthesizer that generate frequencies randomly at a high speed using the DDS technology.

참고문헌 (Reference)

1 Henry T. Nicholas III, "The Optimization of Direct Digital Frequency Synthesizer Performance in the Presence of Finite Word Length Effects IEEE 42st Annual Frequency Control Symposium Digest of Papers" 357-363, 1988

2 NO. 2, "Methods of Mapping from Phase to Sine Amplitude in Direct Digital synthesizer IEEE Transactions On Ultrasonics" 44 (44):

3 Ulrich L. Rohde, "Digital PLL Frequency Synthesizers" Prentice-Hall 1983.

4 Henry T. Nicholas III, "An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation IEEE 41st Annual Frequency Control Symposium Digest of Papers" 495-502, 1987

5 Jouko Vanjja, "A Direct Digital Synthesizer with an On-Chip D/A-Converter IEEE Journal Of Solid-State Circuits" 33 (33): 1998