1 D. R. Welland, "Self-calibration method for capacitors in a monolithic integrated circuit"
2 H. F. Chen, "Self-calibration circuit for capacitance mismatch"
3 K. S. Tan, "On board self-calibration of analog-todigital and digital-to-analog converters"
4 G. Troster, "Error cancellation technique for capacitor arrays in A/D and D/A converters" 35 (35): 749-751, 1988
5 H. Xu, "Analysis and design of regenerative comparators for low offset and noise" 66 (66): 2817-2830, 2019
6 C. P. Hurrell, "An 18 b 12.5 MS/s ADC with 93dB SNR" 45 (45): 2647-2654, 2010
7 J. A. McNeill, "All-digital background calibration of a successive approximation ADC using the"Split ADC"architecture" 58 (58): 2355-2365, 2011
8 M. P. Timko, "A/D converter with charge redistribution DAC and split summation of main and correcting DAC outputs"
9 S. Fateh, "A reconfigurable 5-to-14 bit SAR ADC for battery-powered medical instrumentation" 62 (62): 2685-2694, 2015
10 J. -Y. Um, "A digital-domain calibration of splitcapacitor DAC for a differential SAR ADC without additional analog circuits" 60 (60): 2845-2856, 2013
1 D. R. Welland, "Self-calibration method for capacitors in a monolithic integrated circuit"
2 H. F. Chen, "Self-calibration circuit for capacitance mismatch"
3 K. S. Tan, "On board self-calibration of analog-todigital and digital-to-analog converters"
4 G. Troster, "Error cancellation technique for capacitor arrays in A/D and D/A converters" 35 (35): 749-751, 1988
5 H. Xu, "Analysis and design of regenerative comparators for low offset and noise" 66 (66): 2817-2830, 2019
6 C. P. Hurrell, "An 18 b 12.5 MS/s ADC with 93dB SNR" 45 (45): 2647-2654, 2010
7 J. A. McNeill, "All-digital background calibration of a successive approximation ADC using the"Split ADC"architecture" 58 (58): 2355-2365, 2011
8 M. P. Timko, "A/D converter with charge redistribution DAC and split summation of main and correcting DAC outputs"
9 S. Fateh, "A reconfigurable 5-to-14 bit SAR ADC for battery-powered medical instrumentation" 62 (62): 2685-2694, 2015
10 J. -Y. Um, "A digital-domain calibration of splitcapacitor DAC for a differential SAR ADC without additional analog circuits" 60 (60): 2845-2856, 2013
11 K-. H. Chang, "A calibration-free 13-bit 10-MS/s full-analog SAR ADC with continuous-time feedforward cascaded op-amps" 54 (54): 2691-2702, 2019
12 H. Xu, "A 78. 5-dB SNDR radiation-and metastability-tolerant two-step split SAR ADC operating up to 75 MS/s with 24. 9-mW power consumption in 65-nm CMOS" 54 (54): 441-451, 2019
13 T. -C. Hung, "A 75. 3-dB SNDR 24-MS/s ring amplifier-based pipelined ADC using averaging correlated level shifting and reference swapping for reducing errors from finite opamp gain and capacitor" 54 (54): 1425-1435, 2019
14 W. Liu, "A 600 MS/s 30 mW 0.13μm CMOS ADC array achieving over 60 dB SFDR with adaptive digital equalization" 82-83, 2009
15 M. Ding, "A 46 μW 13 b 6. 4 MS/s SAR ADC with background mismatch and offset calibration" 52 (52): 423-432, 2017
16 M. Ahmadi, "A 3. 3fJ/conversion-step 250 kS/s 10 b SAR ADC using optimized vote allocation" 1 (1): 1-4, 2013
17 S. Asghar, "A 2-MS/s, 11. 22 ENOB, extended input range SAR ADC with improved DNL and offset calculation" 65 (65): 3628-3638, 2018
18 J. Shen, "A 16-bit 16-MS/s SAR ADC with on-chip calibration in 55-nm CMOS" 53 (53): 1149-1160, 2018
19 M. Krämer, "A 14-bit 30-MS/s 38-mW SAR ADC using noise filter gear shifting" 64 (64): 116-120, 2017
20 C. -W. Hsu, "A 12-b 40-MS/s calibration-free SAR ADC" 65 (65): 881-890, 2018
21 J. Park, "A 12-/14-bit, 4/2MSPS, 0.085mm2 SAR ADC in 65nm using novel residue boosting" 1-4, 2017
22 P. Harpe, "A 10b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10. 1b ENOB at 2. 2fJ/conversion-step" 48 (48): 3011-3018, 2013
23 L. Chen, "A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction" 1-4, 2015
24 Y. Zhu, "A 10-bit 100-MS/s reference-free SAR ADC in 90nm CMOS" 45 (45): 1111-1121, 2010
25 M. Yoshioka, "A 10-b 50-MS/s 820-μW SAR ADC with on-chip digital calibration" 384-385, 2010
26 J. -S. Park, "12 b 50 MS/s 0. 18 μm CMOS SAR ADC based on highly linear C-R hybrid DAC" 56 (56): 119-121, 2020