Microarchitects should consider energy consumption, together with performance, when designing instruction cache architecture, especially in embedded processors. This paper proposes a low-power instruction cache architecture, where a modified trace cac...
Microarchitects should consider energy consumption, together with performance, when designing instruction cache architecture, especially in embedded processors. This paper proposes a low-power instruction cache architecture, where a modified trace cache is used for reducing the number of accesses to the main instruction cache.