In this paper, the problem of finding tests to detect faults in combinational logic circuits is considered. At first, the method of fault detection in fan-out-free irredundant circuits is derived, and the result is extended to the fan-out redundant ci...
In this paper, the problem of finding tests to detect faults in combinational logic circuits is considered. At first, the method of fault detection in fan-out-free irredundant circuits is derived, and the result is extended to the fan-out redundant circuits. A fan-out circuit is decomposed into a set of fan-out-free subcircuits by cutting the lines at the internal fan-out points, and the minimal detecting test. sets for each subcircuit are found separately. And then, the compatible tests from each test set are combined maximally into composite tests to generate primary input binary vectors. By this procedure. the minimal complete test sets for reconvergent fan-out circuits are easily found and the detectable and undetectable faults are also classified clearly.