1 송윤귀, "저항 및 커패시턴스 스케일링 구조를 이용한 위상고정루프" 대한전자공학회 46 (46): 37-44, 2009
2 J. Choi, "Hihg multiplication factor capacitor multiplier for an on-chip PLL loop filter" 45 (45): 239-240, 2009
3 I.-C. Hwang, "Area efficient and self-biased capacitor multiplier for on-chip loop filter" 42 (42): 1392-1393, 2006
4 P. K. Hanumolu, "Analysis of Charge-Pump Phase-Locked Loops" 51 (51): 1665-1674, 2004
5 S-R. Han, "A time-constant calibrated phase-locked loop with a fast-locked time" 54 (54): 34-38, 2007
6 Y. Song, "A high-performance OLL with a low-power active switchedcapacitor loop filter" 58 (58): 555-559, 2011
7 Y. Koo, "A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCSand cellualr-CDMA wireless systems" 37 (37): 536-542, 2002
8 J. Craninckx, "A fully integrated CMOS DCS-1800 frequency synthesizer" 33 (33): 2054-2065, 1998
9 L. Liu, "A charge-domain auto-and cross-corrrelation based data synchronization schme with powerand area-efficient PLL for impulse radio UWB receiver" 46 (46): 1349-1359, 2011
10 B. Catli, "A 2sub-200 fs RMS jitter capacotor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications" 1-4, 2013
1 송윤귀, "저항 및 커패시턴스 스케일링 구조를 이용한 위상고정루프" 대한전자공학회 46 (46): 37-44, 2009
2 J. Choi, "Hihg multiplication factor capacitor multiplier for an on-chip PLL loop filter" 45 (45): 239-240, 2009
3 I.-C. Hwang, "Area efficient and self-biased capacitor multiplier for on-chip loop filter" 42 (42): 1392-1393, 2006
4 P. K. Hanumolu, "Analysis of Charge-Pump Phase-Locked Loops" 51 (51): 1665-1674, 2004
5 S-R. Han, "A time-constant calibrated phase-locked loop with a fast-locked time" 54 (54): 34-38, 2007
6 Y. Song, "A high-performance OLL with a low-power active switchedcapacitor loop filter" 58 (58): 555-559, 2011
7 Y. Koo, "A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCSand cellualr-CDMA wireless systems" 37 (37): 536-542, 2002
8 J. Craninckx, "A fully integrated CMOS DCS-1800 frequency synthesizer" 33 (33): 2054-2065, 1998
9 L. Liu, "A charge-domain auto-and cross-corrrelation based data synchronization schme with powerand area-efficient PLL for impulse radio UWB receiver" 46 (46): 1349-1359, 2011
10 B. Catli, "A 2sub-200 fs RMS jitter capacotor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications" 1-4, 2013
11 J. Kim, "A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0. 13-μm CMOS" 41 (41): 899-908, 2006
12 K. Shu, "A 2. 4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacotance multiplier" 358 (358): 866-874, 2003