1 김지현, "이차원 양자 효과를 고려한 극미세 Double-Gate MOSFET 특성 분석" 대한전자공학회 45 (45): 15-22, 2008
2 이치우, "나노 스케일 MuGFET의 소자 구조 최적화에 관한 연구" 대한전자공학회 43 (43): 23-30, 2006
3 Lori Washington, "pMOSFET With 200%Mobility Enhancement Induced by Mutiple Stressors" 27 (27): 511-513, 2006
4 "The International Technology Roadmap for Semiconductors(ITRS)"
5 "Synopsys Sentaurus Device User Guide Ver.H-2013.03"
6 Myung-Dong Ko, "Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis" 60 (60): 2721-2727, 2013
7 Kian-Ming Tan, "Strained p-channel FinFETs with extended pi-shaped silicon-germanium source and drain stressors" 28 (28): 905-908, 2007
8 Kah-Wee Ang, "Strained n-MOSFET with embedded source/drain stressors and strain-transfer structure(STS) for enhanced transistor performance" 55 (55): 850-857, 2008
9 Kehuey Wu, "Performance Advantage and Energy Saving of Triangular-Shaped FinFETs" 143-146, 2013
10 W. Yang, "On the feasibility of nanoscale triple gate CMOS transistors" 52 (52): 1159-1164, 2005
1 김지현, "이차원 양자 효과를 고려한 극미세 Double-Gate MOSFET 특성 분석" 대한전자공학회 45 (45): 15-22, 2008
2 이치우, "나노 스케일 MuGFET의 소자 구조 최적화에 관한 연구" 대한전자공학회 43 (43): 23-30, 2006
3 Lori Washington, "pMOSFET With 200%Mobility Enhancement Induced by Mutiple Stressors" 27 (27): 511-513, 2006
4 "The International Technology Roadmap for Semiconductors(ITRS)"
5 "Synopsys Sentaurus Device User Guide Ver.H-2013.03"
6 Myung-Dong Ko, "Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis" 60 (60): 2721-2727, 2013
7 Kian-Ming Tan, "Strained p-channel FinFETs with extended pi-shaped silicon-germanium source and drain stressors" 28 (28): 905-908, 2007
8 Kah-Wee Ang, "Strained n-MOSFET with embedded source/drain stressors and strain-transfer structure(STS) for enhanced transistor performance" 55 (55): 850-857, 2008
9 Kehuey Wu, "Performance Advantage and Energy Saving of Triangular-Shaped FinFETs" 143-146, 2013
10 W. Yang, "On the feasibility of nanoscale triple gate CMOS transistors" 52 (52): 1159-1164, 2005
11 Tsung-Yang Liow, "N-channel(110)-sidewall strained FinFETs with silicon-carbon source and drain stressors and tensile capping layer" 28 (28): 1014-1017, 2007
12 M. Garcia Bardon, "Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance" 114-115, 2013
13 C. R. Manoj, "Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs" 28 (28): 295-297, 2007
14 N. Serra, "Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs" 1-4, 2009
15 J. M. Rabaey, "Digital Integrated Circuits : A Design Perspective" Prentice Hall 226-, 2004
16 Elio Consoli, "Conditional Push-Pull Pulsed Latches with 726fJ·ps Energy-Delay Product in 65nm CMOS" 482-484, 2012
17 K. W. Lee, "Comparative study of analog performance of multiple fin tri-gate FinFETs" 2012
18 Ohkura, Y., "Analysis of gate currents through high-k dielectrics using a Monte Carlo device simulator" 67-70, 2003
19 C. H. Jan, "A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Desity SoC Applications" 3.1.1-3.1.4, 2012
20 C. Auth, "A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors" 2012
21 노석순, "3D Device simulator를 사용한 공정과 Layout에 따른 FinFET 아날로그 특성 연구" 대한전자공학회 50 (50): 35-42, 2013