A Study on High-k Based Capacitor for Passivation Layer of CMOS Image Sensor = 상보성 금속 산화막 반도체 이미지센서의 패시베이션 층을 위한 고유전율 물질 기반 커패시터의 특성 분석

다국어 초록 (Multilingual Abstract)

As the technology of the CMOS image sensor (CIS), which has become the mainstream among image sensors, has developed, pixels are scaled to increase resolution, resulting in three major problems: reduction in full well capacity, light loss, and crosstalk. Backside illuminated (BSI) structures using a high-k passivation layer were introduced to solve this problem. Still, the dark current problem due to the unstable interface between the high-k material and the substrate had to be solved. In this study, two types of capacitors with metal/insulator/semiconductor structures were fabricated using different insulators. In addition, samples subjected to post-treatments, including forming gas annealing (FGA) and/or H2 plasma
treatment (HPT), were additionally obtained to confirm the improvement of electrical properties after treatment. The measured electrical properties are border/interface trap and fixed oxide charge:the number of traps and fixed oxide charges should be small and large, respectively, to solve the dark current problem. In the 1st experiment using Al2O3/SiO2 bilayer-based capacitors, Al2O3 was deposited only by plasma-enhanced (PE) atomic layer deposition (ALD), and HPT was not applied. SiO2 was additionally adopted, considering that the interface quality was poor when only Al2O3 was used in the previous study. As a result, after the FGA process, the interface trap density significantly decreased by ~75% and more than 95% with and without the SiO2 layer, respectively. However, trade-off characteristics that prevent all quantitative goals from being achieved
simultaneously according to the change of SiO2 thicknesses were confirmed. In the 2nd experiment using HfO2 single layer-based capacitors, more diverse process conditions were applied than in the 1st experiment, where thermal ALD (TALD) and HPT were added. As a result, T-ALD showed better results for interface traps, which is the main reason for using T-ALD as a standard for CMOS when the image sensor is not considered. Nevertheless, in the comprehensive experimental results, all quantitative goals were achieved simultaneously only in the sample fabricated with PEALD and FGA. These results suggest a need to develop PEALD technology for CIS is noteworthy because of the fact that PEALD has won the game and its advantages in CIS, which uses a thick passivation layer.

목차 (Table of Contents)

• I. Introduction ................................................................................................... 1
• 1.1 CMOS Image Sensor vs. Charge-Coupled Device ....................................... 1
• 1.2 Advances and Challenges in CMOS Image Sensor Technology .................... 4
• 1.3 Overview of the Thesis ............................................................................... 6
• REFERENCES ............................................................................................ 8
• II. [Exp. 1] Effects of Post-Treatment on Al2O3/SiO2 Bilayers with Different SiO2
• Thicknesses ................................................................................................ 11
• 2.1 Introduction .......................................................................................... 11
• 2.2 Device Structure and Fabrication Process ................................................. 12
• 2.3 Results and Discussion ........................................................................... 17
• 2.3.1 Transmission Electron Microscopy (TEM) ...................................... 17
• 2.3.2 Border-Trapped Charge ............................................................. 17
• 2.3.3 Interface Trap Density .................................................................. 18
• 2.3.4 Oxide Fixed Charge ..................................................................... 19
• REFERENCES .......................................................................................... 20
• III. [Exp. 2] Effects of Post-Treatments on HfO2 Layers Deposited by Different ALD
• Methods: PEALD or T-ALD ....................................................................... 23
• 3.1 Introduction .......................................................................................... 23
• 3.2 Device Structure and Fabrication Process ................................................. 24
• 3.3 Results and Discussion ........................................................................... 25
• 3.3.1 Interface Trap Density .................................................................. 25
• 3.3.2 Oxide Fixed Charge ..................................................................... 27
• REFERENCES ........................................................................................... 28
• IV. Conclusion ................................................................................................ 29