Optimal high yield SRAM architecture

다국어 초록 (Multilingual Abstract)

The correlation between read access failure cells is changed with architecture because the number of cells corresponding to a sense amplifier and a bit-line tracking path is changed. This change varies the distribution of the number of failure cells and thus the yield of SRAMs. Analytical models are proposed to predict the change of the distribution and the yield. The proposed analytical yield model shows that the column redundancy is more efficient than the row redundancy to improve the yield. The change of the number of architecture components (cell, bit-line tracking path, and sense amplifier) influences on the yield and the yield change is proportional to variances of sense amplifier enable time (TSAE), voltage difference between two bit-lines (ΔVBL), and sense amplifier offset voltage (VOS). On the other hand, the yield trend due to this influence is different according to redundancy usage; non-redundancy, row redundancy, column redundancy, and both row and column redundancies. Therefore, the optimal architecture is changed according to redundancy usage. Moreover, the variances of TSAE, ΔVBL, and VOS due to the process variation become worse with technology scaling, which causes the optimal architecture to be changed and the sensitivity of the yield change to architecture to be increased. The sensitivity of the yield change is also increased with the SRAM capacity. Thus, the optimal architecture must be considered to achieve a high SRAM yield with technology scaling and memory capacity. The proposed analytical yield model is very helpful to estimate the optimal architecture in early SRAM design stage.