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이 학술지의 논문 검색
Clock Skew Determination from Parameter Variations at Chip and Wafer Level
Sauter, S.;Cousinard, D.;Thewes, R.;Schmitt-Landsiedel, D. IEEE 1999 p.7-9
Circuit Performance Variability Decomposition
Orshansky, M.;Spanos, C.;Hu, C. IEEE 1999 p.10-13
Analysis of the Impact of Intra-die Variance on Clock Skew
Zanella, S.;Nardi, A.;Quarantelli, M.;Neviani, A. IEEE 1999 p.14-17
Fault Diagnosis of Analog Integrated Circuits using Response Surface Methods
Vazquez-Gonzalez, J.-L.;Flores-Verdad, G. E. IEEE 1999 p.18-21
A New Filtering Method to Extract Repeated Defects (FIMER)
Imai, K.;Kaga, T. IEEE 1999 p.22-25
Kikuchi, H.;Nishio, N. IEEE 1999 p.26-29
Kato, K.;Ueki, A.;Kaga, T. IEEE 1999 p.30-33
A Systematic and Physical Application of Multivariate Statistics to MOSFET I-V Models
Kondo, M.;Onodera, H.;Tamaru, K. IEEE 1999 p.34-37
TCAD-Prototyping with New Accurate Worst-case Definition for a 0.2 micron CMOS-ASIC Process
Kunitomo, H.;Sato, H.;Tsuneno, K.;Ikematsu, R. IEEE 1999 p.38-41