1 강정명, "이퀄라이저 적응기를 포함한 12.5-Gb/s 저전력 수신단 설계" 대한전자공학회 50 (50): 71-79, 2013
2 Hwan-Wook Park, "Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels" 대한전자공학회 16 (16): 112-117, 2016
3 Y. Zhu, "An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS" 51 (51): 1223-1234, 2016
4 Y. C. Cho, "A Sub-1.0V 20nm 5Gb/s/pin Post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and Adaptive Calibration Scheme For Mobile Application" 240-241, 2013
5 M. Miyahara, "A Low-Noise Self -Calibrating Dynamic Comparator for High -Speed ADCs" 269-272, 2008
6 M. Bucher, "A 6.4-Gbps Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems" 49 (49): 127-139, 2014
7 S. J. Bae, "A 40nm 7Gbps/pin Single-ended Transceiver with Jitter and ISI Reduction Techniques for High-Speed DRAM Interface" 193-194, 2010
8 S. J. Bae, "A 40nm 2Gb 7Gb/s/pin GDDR5SDRAM with a Programmable DQ Ordering Crosstalk Equalizer and Adjustable Clock-Tracking BW" 498-500, 2011
9 T. C. Hsueh, "A 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter with Digital Clock Calibration in 22nm CMOS" 444-445, 2014
10 Y. J. Chen, "A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS" 51 (51): 357-364, 2016
1 강정명, "이퀄라이저 적응기를 포함한 12.5-Gb/s 저전력 수신단 설계" 대한전자공학회 50 (50): 71-79, 2013
2 Hwan-Wook Park, "Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels" 대한전자공학회 16 (16): 112-117, 2016
3 Y. Zhu, "An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS" 51 (51): 1223-1234, 2016
4 Y. C. Cho, "A Sub-1.0V 20nm 5Gb/s/pin Post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and Adaptive Calibration Scheme For Mobile Application" 240-241, 2013
5 M. Miyahara, "A Low-Noise Self -Calibrating Dynamic Comparator for High -Speed ADCs" 269-272, 2008
6 M. Bucher, "A 6.4-Gbps Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems" 49 (49): 127-139, 2014
7 S. J. Bae, "A 40nm 7Gbps/pin Single-ended Transceiver with Jitter and ISI Reduction Techniques for High-Speed DRAM Interface" 193-194, 2010
8 S. J. Bae, "A 40nm 2Gb 7Gb/s/pin GDDR5SDRAM with a Programmable DQ Ordering Crosstalk Equalizer and Adjustable Clock-Tracking BW" 498-500, 2011
9 T. C. Hsueh, "A 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter with Digital Clock Calibration in 22nm CMOS" 444-445, 2014
10 Y. J. Chen, "A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS" 51 (51): 357-364, 2016
11 H. Lee, "A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP- Based DRAM Interface on Si-Carrier Channel" 50 (50): 2613-2624, 2015
12 A. Amirkhany, "A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface" 47 (47): 911-925, 2012
13 Y. S. Kim, "A 110 MHz to 1. 4 GHz Locking 40-Phase All-Digital DLL" 46 (46): 435-444, 2011
14 W. S. Choi, "A 0. 45-to-0. 7V 1-to-6Gbps 0. 29-to-0. 58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS" 66-68, 2015
15 K. Kaviani, "A 0. 4-mW/Gbps Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gbps Source-Series Terminated Transceiver" 48 (48): 636-648, 2013
16 구자현, "13-Gbps 저스윙 저전력 니어-그라운드 시그널링 트랜시버" 대한전자공학회 51 (51): 49-58, 2014