Although the functionality of basic gates and interconnect structures of Quantum-dot Cellular Automata (QCA) has been demonstrated on a physical implementation, and the design entry tools and simulators for it have developed, its design technology is ...
Although the functionality of basic gates and interconnect structures of Quantum-dot Cellular Automata (QCA) has been demonstrated on a physical implementation, and the design entry tools and simulators for it have developed, its design technology is not quite ready for ultra large scale designs which have been implemented by the CMOS technology. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors. After the gate and interconnect structures of the QCA design 라e identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a bit slice of an QCA ALU. The digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.